Jim created this revision. Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, arichardson. Herald added a project: All. Jim requested review of this revision. Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay. Herald added a project: clang.
Apparently, both of clz and ctz should have tests for _32 version on RV64. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D150945 Files: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c @@ -50,6 +50,18 @@ return __builtin_riscv_clz_64(a); } +// RV64ZBB-LABEL: @ctz_32( +// RV64ZBB-NEXT: entry: +// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV64ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 +// RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false) +// RV64ZBB-NEXT: ret i32 [[TMP1]] +// +int ctz_32(int a) { + return __builtin_riscv_ctz_32(a); +} + // RV64ZBB-LABEL: @ctz_64( // RV64ZBB-NEXT: entry: // RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c =================================================================== --- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c +++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c @@ -50,6 +50,18 @@ return __builtin_riscv_clz_64(a); } +// RV64ZBB-LABEL: @ctz_32( +// RV64ZBB-NEXT: entry: +// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 +// RV64ZBB-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4 +// RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4 +// RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false) +// RV64ZBB-NEXT: ret i32 [[TMP1]] +// +int ctz_32(int a) { + return __builtin_riscv_ctz_32(a); +} + // RV64ZBB-LABEL: @ctz_64( // RV64ZBB-NEXT: entry: // RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
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