fakepaper56 created this revision.
Herald added subscribers: jobnoorman, luke, vporpo, VincentWu, vkmr,
frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna,
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01,
edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal,
simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
Herald added a project: All.
fakepaper56 requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD,
MaskRay.
Herald added projects: clang, LLVM.
The patch adds the instructions in Zicfisslp extension. Zicfisslp extension is
to support shadow stack and landing pad for better control flow integrity.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D152793
Files:
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoZicfisslp.td
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/zicfisslp-invalid.s
llvm/test/MC/RISCV/zicfisslp-valid.s
Index: llvm/test/MC/RISCV/zicfisslp-valid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/zicfisslp-valid.s
@@ -0,0 +1,120 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfisslp,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicfisslp,+c -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicfisslp,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfisslp -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicfisslp,+c < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicfisslp -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload x1
+
+# CHECK-ASM-AND-OBJ: ssload x1
+# CHECK-ASM: encoding: [0x73,0xc0,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload ra
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload x5
+
+# CHECK-ASM-AND-OBJ: ssload x5
+# CHECK-ASM: encoding: [0x73,0xc0,0xc2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssload t0
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk x1
+
+# CHECK-ASM-AND-OBJ: sspopchk x1
+# CHECK-ASM: encoding: [0xf3,0x40,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk ra
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk x5
+
+# CHECK-ASM-AND-OBJ: sspopchk x5
+# CHECK-ASM: encoding: [0xf3,0x42,0xc0,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspopchk t0
+
+# CHECK-ASM-AND-OBJ: sspinc 4
+# CHECK-ASM: encoding: [0x73,0x40,0xd2,0x81]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspinc 4
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspush x1
+
+# CHECK-ASM-AND-OBJ: sspush ra
+# CHECK-ASM: encoding: [0x73,0x40,0x10,0x8a]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+sspush ra
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'zicfisslp' (shadow-stack and landing-pads)
+sspush x5
+
+# check-asm-and-obj: sspush t0
+# check-asm: encoding: [0x73,0x40,0x50,0x8a]
+# check-no-ext: error: instruction requires the following: 'zicfisslp' (shadow-stack and landing-pads)
+sspush t0
+
+# CHECK-ASM-AND-OBJ: ssprr ra
+# CHECK-ASM: encoding: [0xf3,0x40,0x00,0x86]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssprr ra
+
+# CHECK-ASM-AND-OBJ: ssamoswap t0, zero, (a0)
+# CHECK-ASM: encoding: [0xf3,0x42,0x05,0x82]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+ssamoswap t0, x0, (a0)
+
+# CHECK-ASM-AND-OBJ: c.sspush x1
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfisslp' (Shadow-stack and Landing-pads)
+c.sspush x1
+
+# CHECK-ASM-AND-OBJ: c.sspush x1
+# CHECK-ASM: encoding: [0x81,0x60]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfisslp' (Shadow-stack and Landing-pads)
+c.sspush ra
+
+# CHECK-ASM-AND-OBJ: c.sspopchk x5
+# CHECK-ASM: encoding: [0x81,0x62]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfisslp' (Shadow-stack and Landing-pads)
+c.sspopchk x5
+
+# CHECK-ASM-AND-OBJ: c.sspopchk x5
+# CHECK-ASM: encoding: [0x81,0x62]
+# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions), 'Zicfisslp' (Shadow-stack and Landing-pads)
+c.sspopchk t0
+
+# CHECK-ASM-AND-OBJ: lpcll 682
+# CHECK-ASM: encoding: [0x73,0x40,0x55,0x83]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+lpcll 0x2AA
+
+# CHECK-ASM-AND-OBJ: lpcnl 955
+# CHECK-ASM: encoding: [0x73,0xc0,0xdd,0x87]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zicfisslp' (Shadow-stack and Landing-pads)
+lpcnl 0x3BB
Index: llvm/test/MC/RISCV/zicfisslp-invalid.s
===================================================================
--- /dev/null
+++ llvm/test/MC/RISCV/zicfisslp-invalid.s
@@ -0,0 +1,34 @@
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfisslp,+c -riscv-no-aliases -show-encoding \
+# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
+# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-zicfisslp,+c -riscv-no-aliases -show-encoding \
+# RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ERR %s
+
+# CHECK-ERR: error: invalid operand for instruction
+ssload a0
+
+# CHECK-ERR: error: invalid operand for instruction
+sspopchk a1
+
+# CHECK-ERR: error: invalid operand for instruction
+c.sspush t0
+
+# CHECK-ERR: error: invalid operand for instruction
+c.sspopchk ra
+
+# CHECK-ERR: error: immediate must be an integer in the range [1, 31]
+sspinc 32
+
+# CHECK-ERR: error: invalid operand for instruction
+sspush a0
+
+# CHECK-ERR: error: invalid operand for instruction
+ssprr zero
+
+# CHECK-ERR: error: invalid operand for instruction
+ssamoswap zero, x0, (a0)
+
+# CHECK-ERR: error: immediate must be an integer in the range [0, 1023]
+lpcll 0x4AA
+
+# CHECK-ERR: error: immediate must be an integer in the range [0, 1023]
+lpcnl 0x4AA
Index: llvm/test/MC/RISCV/attribute-arch.s
===================================================================
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -278,3 +278,6 @@
.attribute arch, "rv32i_zvfbfwma0p6"
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"
+
+.attribute arch, "rv32i_zicfisslp0p1"
+# CHECK: .attribute 5, "rv32i2p1_zicfisslp0p1"
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -183,6 +183,10 @@
let RegInfos = XLenRI;
}
+def GPRRA : RegisterClass<"RISCV", [XLenVT], 32, (add X1, X5)> {
+ let RegInfos = XLenRI;
+}
+
// Floating point registers
let RegAltNameIndices = [ABIRegAltName] in {
def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
@@ -589,3 +593,6 @@
// Special registers
def FFLAGS : RISCVReg<0, "fflags">;
def FRM : RISCVReg<0, "frm">;
+
+// Shadow Stack register
+def SSP : RISCVReg<0, "ssp">;
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZicfisslp.td
===================================================================
--- /dev/null
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZicfisslp.td
@@ -0,0 +1,132 @@
+//===-- RISCVInstrInfoZ.td - RISC-V CFG -*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand definitions.
+//===----------------------------------------------------------------------===//
+
+def uimm5nonzero : Operand<XLenVT>,
+ ImmLeaf<XLenVT, [{return (Imm != 0) && isUInt<5>(Imm);}]> {
+ let ParserMatchClass = UImmAsmOperand<5, "NonZero">;
+ let EncoderMethod = "getImmOpValue";
+ let DecoderMethod = "decodeUImmNonZeroOperand<5>";
+ let OperandType = "OPERAND_UIMM5_NONZERO";
+ let OperandNamespace = "RISCVOp";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return (Imm != 0) && isUInt<5>(Imm);
+ return MCOp.isBareSymbolRef();
+ }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let Uses = [SSP] in {
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class RV_SSPop<bits<5> rd, bits<5> rs1, string opcodestr, string argstr> :
+ RVInst<(outs GPR:$rd), (ins GPR:$rs1), opcodestr, argstr, [], InstFormatI> {
+ let Inst{31-20} = 0b100000011100;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = OPC_SYSTEM.Value;
+}
+} // Uses = [SSP]
+
+class RVC_SSInst<bits<5> rs1, string opcodestr, string argstr> :
+ RVInst16<(outs), (ins:$rs1), opcodestr, argstr, [], InstFormatOther> {
+ let Inst{15-13} = 0b011;
+ let Inst{12} = 0;
+ let Inst{11-7} = rs1;
+ let Inst{6-2} = 0b00000;
+ let Inst{1-0} = 0b01;
+}
+
+let Uses = [X7], hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+class RV_LPInst<bits<7> funct7, string opcodestr> :
+ RVInst<(outs), (ins uimm10:$uimm10), opcodestr, "$uimm10", [], InstFormatOther> {
+ bits<10> uimm10;
+ let Inst{31-25} = funct7;
+ let Inst{24-15} = uimm10;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = 0b00000;
+ let Inst{6-0} = OPC_SYSTEM.Value;
+}
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZicfisslp] in {
+def SSLoadX1: RV_SSPop<0b00000, 0b00001, "ssload", "x1">;
+def SSLoadX5: RV_SSPop<0b00000, 0b00101, "ssload", "x5">;
+def SSPopChkX1: RV_SSPop<0b00001, 0b00000, "sspopchk", "x1">;
+def SSPopChkX5: RV_SSPop<0b00101, 0b00000, "sspopchk", "x5">;
+
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def SSPINC : RVInst<(outs), (ins uimm5nonzero:$imm), "sspinc", "$imm", [], InstFormatI> {
+ bits<5> imm;
+ let Inst{31-20} = 0b100000011101;
+ let Inst{19-15} = imm;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = 0b00000;
+ let Inst{6-0} = OPC_SYSTEM.Value;
+}
+
+def SSPRR : RVInst<(outs GPRNoX0:$rd), (ins), "ssprr", "$rd", [], InstFormatR> {
+ bits<5> rd;
+ let Inst{31-25} = 0b1000011;
+ let Inst{24-20} = 0b00000;
+ let Inst{19-15} = 0b00000;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = OPC_SYSTEM.Value;
+}
+} // Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+def SSPUSH : RVInst<(outs), (ins GPRRA:$rs2), "sspush", "$rs2", [], InstFormatR> {
+ bits<5> rs2;
+ let Inst{31-25} = 0b1000101;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = 0b00000;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = 0b00000;
+ let Inst{6-0} = OPC_SYSTEM.Value;
+}
+
+def SSAMOSWAP :
+ RVInst<(outs GPRNoX0:$dest), (ins GPR:$addr, GPR:$src),
+ "ssamoswap", "$dest, $src, (${addr})", [], InstFormatR> {
+ bits<5> dest;
+ bits<5> src;
+ bits<5> addr;
+ let Inst{31-25} = 0b1000001;
+ let Inst{24-20} = src;
+ let Inst{19-15} = addr;
+ let Inst{14-12} = 0b100;
+ let Inst{11-7} = dest;
+ let Inst{6-0} = OPC_SYSTEM.Value;
+}
+} // Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1
+} // Predicates = [HasStdExtZicfisslp]
+
+let Predicates = [HasStdExtZicfisslp, HasStdExtC] in {
+let Uses = [SSP], Defs = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def C_SSPUSHX1 : RVC_SSInst<0b00001, "c.sspush", "x1">;
+
+let Uses = [SSP], hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def C_SSPopChkX5 : RVC_SSInst<0b00101, "c.sspopchk", "x5">;
+}// Predicates = [HasStdExtZicfisslp, HasStdExtC]
+
+let Predicates = [HasStdExtZicfisslp] in {
+def LPCLL : RV_LPInst<0b1000001, "lpcll">;
+def LPCNL : RV_LPInst<0b1000011, "lpcnl">;
+} // Predicates = [HasStdExtZicfisslp]
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -230,6 +230,13 @@
let OperandNamespace = "RISCVOp";
}
+def uimm10 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]> {
+ let ParserMatchClass = UImmAsmOperand<10>;
+ let DecoderMethod = "decodeUImmOperand<10>";
+ let OperandType = "OPERAND_UIMM10";
+ let OperandNamespace = "RISCVOp";
+}
+
def InsnDirectiveOpcode : AsmOperandClass {
let Name = "InsnDirectiveOpcode";
let ParserMethod = "parseInsnDirectiveOpcode";
@@ -1911,6 +1918,7 @@
include "RISCVInstrInfoZfh.td"
include "RISCVInstrInfoZicbo.td"
include "RISCVInstrInfoZicond.td"
+include "RISCVInstrInfoZicfisslp.td"
//===----------------------------------------------------------------------===//
// Vendor extensions
Index: llvm/lib/Target/RISCV/RISCVFeatures.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVFeatures.td
+++ llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -79,6 +79,13 @@
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
+def FeatureStdExtZicfisslp
+ : SubtargetFeature<"experimental-zicfisslp", "HasStdExtZicfisslp", "true",
+ "'zicfisslp' (Shadow-stack and Landing-pads)">;
+def HasStdExtZicfisslp : Predicate<"Subtarget->hasStdExtZicfisslp()">,
+ AssemblerPredicate<(all_of FeatureStdExtZicfisslp),
+ "'Zicfisslp' (Shadow-stack and Landing-pads)">;
+
def FeatureStdExtZifencei
: SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
"'zifencei' (fence.i)">;
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -239,6 +239,7 @@
OPERAND_UIMM3,
OPERAND_UIMM4,
OPERAND_UIMM5,
+ OPERAND_UIMM5_NONZERO,
OPERAND_UIMM6,
OPERAND_UIMM7,
OPERAND_UIMM7_LSB00,
@@ -247,6 +248,7 @@
OPERAND_UIMM8_LSB000,
OPERAND_UIMM8_GE32,
OPERAND_UIMM9_LSB000,
+ OPERAND_UIMM10,
OPERAND_UIMM10_LSB00_NONZERO,
OPERAND_UIMM12,
OPERAND_ZERO,
Index: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
===================================================================
--- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -74,6 +74,17 @@
return MCDisassembler::Success;
}
+static DecodeStatus DecodeGPRRARegisterClass(MCInst &Inst, uint32_t RegNo,
+ uint64_t Address,
+ const MCDisassembler *Decoder) {
+ MCRegister Reg = RISCV::X0 + RegNo;
+ if (Reg != RISCV::X1 && Reg != RISCV::X5)
+ return MCDisassembler::Fail;
+
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -649,6 +649,18 @@
bool isUImm6() const { return IsUImm<6>(); }
bool isUImm7() const { return IsUImm<7>(); }
bool isUImm8() const { return IsUImm<8>(); }
+ bool isUImm10() const { return IsUImm<10>(); }
+
+ bool isUImm5NonZero() const {
+ if (!isImm())
+ return false;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ int64_t Imm;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ return IsConstantImm && Imm != 0 &&
+ isUInt<5>(fixImmediateForRV32(Imm, isRV64Imm())) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
+ }
bool isUImm8GE32() const {
int64_t Imm;
@@ -1384,12 +1396,16 @@
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
case Match_InvalidUImm5:
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
+ case Match_InvalidUImm5NonZero:
+ return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
case Match_InvalidUImm6:
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1);
case Match_InvalidUImm7:
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 7) - 1);
case Match_InvalidUImm8:
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 8) - 1);
+ case Match_InvalidUImm10:
+ return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 10) - 1);
case Match_InvalidUImm8GE32:
return generateImmOutOfRangeError(Operands, ErrorInfo, 32, (1 << 8) - 1);
case Match_InvalidSImm5:
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -139,11 +139,13 @@
{"ssaia", RISCVExtensionVersion{1, 0}},
{"zihintntl", RISCVExtensionVersion{0, 2}},
+ {"zicfisslp", RISCVExtensionVersion{0, 1}},
{"zca", RISCVExtensionVersion{1, 0}},
{"zcb", RISCVExtensionVersion{1, 0}},
{"zcd", RISCVExtensionVersion{1, 0}},
{"zcf", RISCVExtensionVersion{1, 0}},
+ {"zicfsslp", RISCVExtensionVersion{1, 0}},
{"zcmp", RISCVExtensionVersion{1, 0}},
{"zcmt", RISCVExtensionVersion{1, 0}},
{"zfa", RISCVExtensionVersion{0, 2}},
Index: clang/test/Preprocessor/riscv-target-features.c
===================================================================
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -72,6 +72,7 @@
// CHECK-NOT: __riscv_zfbfmin {{.*$}}
// CHECK-NOT: __riscv_zvfbfmin {{.*$}}
// CHECK-NOT: __riscv_zvfbfwma {{.*$}}
+// CHECK-NOT: __riscv_zicfisslp {{.*$}}
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
// RUN: -o - | FileCheck %s
@@ -719,3 +720,11 @@
// RUN: -march=rv64ifzvfbfwma0p6 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFWMA-EXT %s
// CHECK-ZVFBFWMA-EXT: __riscv_zvfbfwma 6000{{$}}
+
+// RUN: %clang -target riscv32 -menable-experimental-extensions \
+// RUN: -march=rv32izicfisslp0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISSLP-EXT %s
+// RUN: %clang -target riscv64 -menable-experimental-extensions \
+// RUN: -march=rv64izicfisslp0p1 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISSLP-EXT %s
+// CHECK-ZICFISSLP-EXT: __riscv_zicfisslp 1000{{$}}
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
