bryanpkc updated this revision to Diff 531949.
bryanpkc added a comment.
Instead of defining new type flags, `EmitAArch64SMEBuiltinExpr` is updated to
switch on `BuiltinID`, as suggested by @sdesmalen.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D134678/new/
https://reviews.llvm.org/D134678
Files:
clang/include/clang/Basic/arm_sme.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/CodeGen/CodeGenFunction.h
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
Index: clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
===================================================================
--- clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
+++ clang/test/Sema/aarch64-sme-intrinsics/acle_sme_imm.cpp
@@ -187,6 +187,11 @@
// expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
SVE_ACLE_FUNC(svst1_ver_vnum_za8,,,)(0, -1, 16, pg, ptr, 1);
+ // expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
+ SVE_ACLE_FUNC(svldr_vnum_za,,,)(-1, 16, ptr);
+ // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
+ SVE_ACLE_FUNC(svstr_vnum_za,,,)(-1, -1, ptr);
+
// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 15]}}
SVE_ACLE_FUNC(svread_hor_za128, _s8, _m,)(svundef_s8(), pg, -1, -1, 0);
// expected-error@+1 {{argument value 16 is outside the valid range [0, 15]}}
@@ -224,6 +229,9 @@
SVE_ACLE_FUNC(svst1_hor_vnum_za32,,,)(u64, u64, 0, pg, ptr, u64); // expected-error {{argument to 'svst1_hor_vnum_za32' must be a constant integer}}
SVE_ACLE_FUNC(svst1_ver_vnum_za64,,,)(0, u64, u64, pg, ptr, u64); // expected-error {{argument to 'svst1_ver_vnum_za64' must be a constant integer}}
+ SVE_ACLE_FUNC(svldr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svldr_vnum_za' must be a constant integer}}
+ SVE_ACLE_FUNC(svstr_vnum_za,,,)(u64, u64, ptr); // expected-error {{argument to 'svstr_vnum_za' must be a constant integer}}
+
SVE_ACLE_FUNC(svread_hor_za8, _s8, _m,)(svundef_s8(), pg, 0, u64, u64); // expected-error-re {{argument to 'svread_hor_za8{{.*}}_m' must be a constant integer}}
SVE_ACLE_FUNC(svread_ver_za16, _s16, _m,)(svundef_s16(), pg, u64, u64, 0); // expected-error-re {{argument to 'svread_ver_za16{{.*}}_m' must be a constant integer}}
SVE_ACLE_FUNC(svwrite_hor_za32, _s32, _m,)(0, u64, u64, pg, svundef_s32()); // expected-error-re {{argument to 'svwrite_hor_za32{{.*}}_m' must be a constant integer}}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
@@ -0,0 +1,29 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include <arm_sme_draft_spec_subject_to_change.h>
+
+// CHECK-C-LABEL: @test_svstr_vnum_za(
+// CHECK-CXX-LABEL: @_Z18test_svstr_vnum_zajPv(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]])
+// CHECK-NEXT: ret void
+//
+void test_svstr_vnum_za(uint32_t slice_base, void *ptr) {
+ svstr_vnum_za(slice_base, 0, ptr);
+}
+
+// CHECK-C-LABEL: @test_svstr_vnum_za_1(
+// CHECK-CXX-LABEL: @_Z20test_svstr_vnum_za_1jPv(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CHECK-NEXT: [[MULVL:%.*]] = mul nuw nsw i64 [[VSCALE]], 240
+// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT: tail call void @llvm.aarch64.sme.str(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CHECK-NEXT: ret void
+//
+void test_svstr_vnum_za_1(uint32_t slice_base, void *ptr) {
+ svstr_vnum_za(slice_base, 15, ptr);
+}
Index: clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
@@ -0,0 +1,29 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include <arm_sme_draft_spec_subject_to_change.h>
+
+// CHECK-C-LABEL: @test_svldr_vnum_za(
+// CHECK-CXX-LABEL: @_Z18test_svldr_vnum_zajPKv(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: tail call void @llvm.aarch64.sme.ldr(i32 [[SLICE_BASE:%.*]], ptr [[PTR:%.*]])
+// CHECK-NEXT: ret void
+//
+void test_svldr_vnum_za(uint32_t slice_base, const void *ptr) {
+ svldr_vnum_za(slice_base, 0, ptr);
+}
+
+// CHECK-C-LABEL: @test_svldr_vnum_za_1(
+// CHECK-CXX-LABEL: @_Z20test_svldr_vnum_za_1jPKv(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[VSCALE:%.*]] = tail call i64 @llvm.vscale.i64()
+// CHECK-NEXT: [[MULVL:%.*]] = mul nuw nsw i64 [[VSCALE]], 240
+// CHECK-NEXT: [[TMP0:%.*]] = getelementptr i8, ptr [[PTR:%.*]], i64 [[MULVL]]
+// CHECK-NEXT: tail call void @llvm.aarch64.sme.ldr(i32 [[SLICE_BASE:%.*]], ptr [[TMP0]])
+// CHECK-NEXT: ret void
+//
+void test_svldr_vnum_za_1(uint32_t slice_base, const void *ptr) {
+ svldr_vnum_za(slice_base, 15, ptr);
+}
Index: clang/lib/CodeGen/CodeGenFunction.h
===================================================================
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -4269,6 +4269,9 @@
llvm::Value *EmitSMEZero(SVETypeFlags TypeFlags,
llvm::SmallVectorImpl<llvm::Value *> &Ops,
unsigned IntID);
+ llvm::Value *EmitSMELdrStr(SVETypeFlags TypeFlags,
+ llvm::SmallVectorImpl<llvm::Value *> &Ops,
+ unsigned IntID);
llvm::Value *EmitAArch64SMEBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
llvm::Value *EmitAArch64BuiltinExpr(unsigned BuiltinID, const CallExpr *E,
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -9474,6 +9474,21 @@
return Builder.CreateCall(F, Ops);
}
+Value *CodeGenFunction::EmitSMELdrStr(SVETypeFlags TypeFlags,
+ SmallVectorImpl<Value *> &Ops,
+ unsigned IntID) {
+ Function *Vscale = CGM.getIntrinsic(Intrinsic::vscale, Int64Ty);
+ llvm::Value *VscaleCall = Builder.CreateCall(Vscale, {}, "vscale");
+ llvm::Value *MulVL = Builder.CreateMul(
+ VscaleCall,
+ Builder.getInt64(16 * cast<llvm::ConstantInt>(Ops[1])->getZExtValue()),
+ "mulvl");
+ Ops[2] = Builder.CreateGEP(Int8Ty, Ops[2], MulVL);
+ Ops.erase(&Ops[1]);
+ Function *F = CGM.getIntrinsic(IntID, {});
+ return Builder.CreateCall(F, Ops);
+}
+
// Limit the usage of scalable llvm IR generated by the ACLE by using the
// sve dup.x intrinsic instead of IRBuilder::CreateVectorSplat.
Value *CodeGenFunction::EmitSVEDupX(Value *Scalar, llvm::Type *Ty) {
@@ -9937,6 +9952,9 @@
else if (BuiltinID == SME::BI__builtin_sme_svzero_mask_za ||
BuiltinID == SME::BI__builtin_sme_svzero_za)
return EmitSMEZero(TypeFlags, Ops, Builtin->LLVMIntrinsic);
+ else if (BuiltinID == SME::BI__builtin_sme_svldr_vnum_za ||
+ BuiltinID == SME::BI__builtin_sme_svstr_vnum_za)
+ return EmitSMELdrStr(TypeFlags, Ops, Builtin->LLVMIntrinsic);
/// Should not happen
return nullptr;
Index: clang/include/clang/Basic/arm_sme.td
===================================================================
--- clang/include/clang/Basic/arm_sme.td
+++ clang/include/clang/Basic/arm_sme.td
@@ -44,6 +44,11 @@
defm SVLD1_ZA64 : ZALoad<"za64", "l", "aarch64_sme_ld1d", [ImmCheck<0, ImmCheck0_7>, ImmCheck<2, ImmCheck0_1>]>;
defm SVLD1_ZA128 : ZALoad<"za128", "q", "aarch64_sme_ld1q", [ImmCheck<0, ImmCheck0_15>, ImmCheck<2, ImmCheck0_0>]>;
+def SVLDR_VNUM_ZA : MInst<"svldr_vnum_za", "vmiQ", "",
+ [IsOverloadNone, IsStreamingCompatible, IsSharedZA],
+ MemEltTyDefault, "aarch64_sme_ldr",
+ [ImmCheck<1, ImmCheck0_15>]>;
+
////////////////////////////////////////////////////////////////////////////////
// Stores
@@ -73,6 +78,11 @@
defm SVST1_ZA64 : ZAStore<"za64", "l", "aarch64_sme_st1d", [ImmCheck<0, ImmCheck0_7>, ImmCheck<2, ImmCheck0_1>]>;
defm SVST1_ZA128 : ZAStore<"za128", "q", "aarch64_sme_st1q", [ImmCheck<0, ImmCheck0_15>, ImmCheck<2, ImmCheck0_0>]>;
+def SVSTR_VNUM_ZA : MInst<"svstr_vnum_za", "vmi%", "",
+ [IsOverloadNone, IsStreamingCompatible, IsSharedZA, IsPreservesZA],
+ MemEltTyDefault, "aarch64_sme_str",
+ [ImmCheck<1, ImmCheck0_15>]>;
+
////////////////////////////////////////////////////////////////////////////////
// Read horizontal/vertical ZA slices
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