Author: Craig Topper Date: 2023-06-22T11:25:47-07:00 New Revision: e4a93d80f425114e4d943ba176b34590c8d0fece
URL: https://github.com/llvm/llvm-project/commit/e4a93d80f425114e4d943ba176b34590c8d0fece DIFF: https://github.com/llvm/llvm-project/commit/e4a93d80f425114e4d943ba176b34590c8d0fece.diff LOG: [RISCV] Sort the extensions in SupportedExtensions and SupportedExperimentalExtensions. As the extension list continues to grow it probably makes sense to use a binary search rather than linear search. Sorting the strings will make this possible. This also avoids any question about where to add new strings in the tables. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D153170 Added: Modified: clang/test/Driver/riscv-march-mcpu-mtune.c llvm/lib/Support/RISCVISAInfo.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/riscv-march-mcpu-mtune.c b/clang/test/Driver/riscv-march-mcpu-mtune.c index 90b7173974a29..46a2bf8653065 100644 --- a/clang/test/Driver/riscv-march-mcpu-mtune.c +++ b/clang/test/Driver/riscv-march-mcpu-mtune.c @@ -58,9 +58,9 @@ // RUN: | FileCheck -check-prefix=MCPU-E31-MARCH-RV32I %s // MCPU-E31-MARCH-RV32I: "-target-cpu" "sifive-e31" // MCPU-E31-MARCH-RV32I: "-target-feature" "+c" -// MCPU-E31-MARCH-RV32I: "-target-feature" "-m" // MCPU-E31-MARCH-RV32I: "-target-feature" "-a" // MCPU-E31-MARCH-RV32I: "-target-feature" "-f" +// MCPU-E31-MARCH-RV32I: "-target-feature" "-m" // -mcpu, -march and -mtune are given, so pipeline model take from -mtune // and arch ext. take from -march, -mcpu is unused. @@ -68,7 +68,7 @@ // RUN: | FileCheck -check-prefix=MCPU-E31-MTUNE-E76-MARCH-RV32I %s // MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-cpu" "sifive-e31" // MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "+c" -// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-m" // MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-a" // MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-f" +// MCPU-E31-MTUNE-E76-MARCH-RV32I: "-target-feature" "-m" // MCPU-E31-MTUNE-E76-MARCH-RV32I: "-tune-cpu" "sifive-e76" diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 6ceb41a111339..489b308b30d47 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -16,6 +16,7 @@ #include "llvm/Support/raw_ostream.h" #include <array> +#include <atomic> #include <optional> #include <string> #include <vector> @@ -33,6 +34,10 @@ struct RISCVSupportedExtension { const char *Name; /// Supported version. RISCVExtensionVersion Version; + + bool operator<(const RISCVSupportedExtension &RHS) const { + return StringRef(Name) < StringRef(RHS.Name); + } }; } // end anonymous namespace @@ -43,18 +48,47 @@ static const char *RISCVGImplications[] = { "i", "m", "a", "f", "d", "zicsr", "zifencei" }; +// NOTE: This table should be sorted alphabetically by extension name. static const RISCVSupportedExtension SupportedExtensions[] = { - {"i", RISCVExtensionVersion{2, 1}}, - {"e", RISCVExtensionVersion{2, 0}}, - {"m", RISCVExtensionVersion{2, 0}}, {"a", RISCVExtensionVersion{2, 1}}, - {"f", RISCVExtensionVersion{2, 2}}, - {"d", RISCVExtensionVersion{2, 2}}, {"c", RISCVExtensionVersion{2, 0}}, - + {"d", RISCVExtensionVersion{2, 2}}, + {"e", RISCVExtensionVersion{2, 0}}, + {"f", RISCVExtensionVersion{2, 2}}, {"h", RISCVExtensionVersion{1, 0}}, + {"i", RISCVExtensionVersion{2, 1}}, + {"m", RISCVExtensionVersion{2, 0}}, - {"zihintpause", RISCVExtensionVersion{2, 0}}, + {"svinval", RISCVExtensionVersion{1, 0}}, + {"svnapot", RISCVExtensionVersion{1, 0}}, + {"svpbmt", RISCVExtensionVersion{1, 0}}, + + {"v", RISCVExtensionVersion{1, 0}}, + + // vendor-defined ('X') extensions + {"xsfvcp", RISCVExtensionVersion{1, 0}}, + {"xtheadba", RISCVExtensionVersion{1, 0}}, + {"xtheadbb", RISCVExtensionVersion{1, 0}}, + {"xtheadbs", RISCVExtensionVersion{1, 0}}, + {"xtheadcmo", RISCVExtensionVersion{1, 0}}, + {"xtheadcondmov", RISCVExtensionVersion{1, 0}}, + {"xtheadfmemidx", RISCVExtensionVersion{1, 0}}, + {"xtheadmac", RISCVExtensionVersion{1, 0}}, + {"xtheadmemidx", RISCVExtensionVersion{1, 0}}, + {"xtheadmempair", RISCVExtensionVersion{1, 0}}, + {"xtheadsync", RISCVExtensionVersion{1, 0}}, + {"xtheadvdot", RISCVExtensionVersion{1, 0}}, + {"xventanacondops", RISCVExtensionVersion{1, 0}}, + + {"zawrs", RISCVExtensionVersion{1, 0}}, + + {"zba", RISCVExtensionVersion{1, 0}}, + {"zbb", RISCVExtensionVersion{1, 0}}, + {"zbc", RISCVExtensionVersion{1, 0}}, + {"zbkb", RISCVExtensionVersion{1, 0}}, + {"zbkc", RISCVExtensionVersion{1, 0}}, + {"zbkx", RISCVExtensionVersion{1, 0}}, + {"zbs", RISCVExtensionVersion{1, 0}}, {"zca", RISCVExtensionVersion{1, 0}}, {"zcb", RISCVExtensionVersion{1, 0}}, @@ -63,101 +97,78 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"zcmp", RISCVExtensionVersion{1, 0}}, {"zcmt", RISCVExtensionVersion{1, 0}}, - {"zfhmin", RISCVExtensionVersion{1, 0}}, - {"zfh", RISCVExtensionVersion{1, 0}}, + {"zdinx", RISCVExtensionVersion{1, 0}}, + {"zfh", RISCVExtensionVersion{1, 0}}, + {"zfhmin", RISCVExtensionVersion{1, 0}}, {"zfinx", RISCVExtensionVersion{1, 0}}, - {"zdinx", RISCVExtensionVersion{1, 0}}, - {"zhinxmin", RISCVExtensionVersion{1, 0}}, + {"zhinx", RISCVExtensionVersion{1, 0}}, + {"zhinxmin", RISCVExtensionVersion{1, 0}}, - {"zba", RISCVExtensionVersion{1, 0}}, - {"zbb", RISCVExtensionVersion{1, 0}}, - {"zbc", RISCVExtensionVersion{1, 0}}, - {"zbs", RISCVExtensionVersion{1, 0}}, + {"zicbom", RISCVExtensionVersion{1, 0}}, + {"zicbop", RISCVExtensionVersion{1, 0}}, + {"zicboz", RISCVExtensionVersion{1, 0}}, + {"zicntr", RISCVExtensionVersion{1, 0}}, + {"zicsr", RISCVExtensionVersion{2, 0}}, + {"zifencei", RISCVExtensionVersion{2, 0}}, + {"zihintpause", RISCVExtensionVersion{2, 0}}, + {"zihpm", RISCVExtensionVersion{1, 0}}, - {"zbkb", RISCVExtensionVersion{1, 0}}, - {"zbkc", RISCVExtensionVersion{1, 0}}, - {"zbkx", RISCVExtensionVersion{1, 0}}, + {"zk", RISCVExtensionVersion{1, 0}}, + {"zkn", RISCVExtensionVersion{1, 0}}, {"zknd", RISCVExtensionVersion{1, 0}}, {"zkne", RISCVExtensionVersion{1, 0}}, {"zknh", RISCVExtensionVersion{1, 0}}, - {"zksed", RISCVExtensionVersion{1, 0}}, - {"zksh", RISCVExtensionVersion{1, 0}}, {"zkr", RISCVExtensionVersion{1, 0}}, - {"zkn", RISCVExtensionVersion{1, 0}}, {"zks", RISCVExtensionVersion{1, 0}}, + {"zksed", RISCVExtensionVersion{1, 0}}, + {"zksh", RISCVExtensionVersion{1, 0}}, {"zkt", RISCVExtensionVersion{1, 0}}, - {"zk", RISCVExtensionVersion{1, 0}}, {"zmmul", RISCVExtensionVersion{1, 0}}, - {"v", RISCVExtensionVersion{1, 0}}, - {"zvl32b", RISCVExtensionVersion{1, 0}}, - {"zvl64b", RISCVExtensionVersion{1, 0}}, - {"zvl128b", RISCVExtensionVersion{1, 0}}, - {"zvl256b", RISCVExtensionVersion{1, 0}}, - {"zvl512b", RISCVExtensionVersion{1, 0}}, + {"zve32f", RISCVExtensionVersion{1, 0}}, + {"zve32x", RISCVExtensionVersion{1, 0}}, + {"zve64d", RISCVExtensionVersion{1, 0}}, + {"zve64f", RISCVExtensionVersion{1, 0}}, + {"zve64x", RISCVExtensionVersion{1, 0}}, {"zvl1024b", RISCVExtensionVersion{1, 0}}, - {"zvl2048b", RISCVExtensionVersion{1, 0}}, - {"zvl4096b", RISCVExtensionVersion{1, 0}}, - {"zvl8192b", RISCVExtensionVersion{1, 0}}, + {"zvl128b", RISCVExtensionVersion{1, 0}}, {"zvl16384b", RISCVExtensionVersion{1, 0}}, + {"zvl2048b", RISCVExtensionVersion{1, 0}}, + {"zvl256b", RISCVExtensionVersion{1, 0}}, {"zvl32768b", RISCVExtensionVersion{1, 0}}, + {"zvl32b", RISCVExtensionVersion{1, 0}}, + {"zvl4096b", RISCVExtensionVersion{1, 0}}, + {"zvl512b", RISCVExtensionVersion{1, 0}}, + {"zvl64b", RISCVExtensionVersion{1, 0}}, {"zvl65536b", RISCVExtensionVersion{1, 0}}, - {"zve32x", RISCVExtensionVersion{1, 0}}, - {"zve32f", RISCVExtensionVersion{1, 0}}, - {"zve64x", RISCVExtensionVersion{1, 0}}, - {"zve64f", RISCVExtensionVersion{1, 0}}, - {"zve64d", RISCVExtensionVersion{1, 0}}, - - {"zicbom", RISCVExtensionVersion{1, 0}}, - {"zicboz", RISCVExtensionVersion{1, 0}}, - {"zicbop", RISCVExtensionVersion{1, 0}}, - {"zicntr", RISCVExtensionVersion{1, 0}}, - {"zicsr", RISCVExtensionVersion{2, 0}}, - {"zifencei", RISCVExtensionVersion{2, 0}}, - {"zihpm", RISCVExtensionVersion{1, 0}}, - - {"zawrs", RISCVExtensionVersion{1, 0}}, - - {"svnapot", RISCVExtensionVersion{1, 0}}, - {"svpbmt", RISCVExtensionVersion{1, 0}}, - {"svinval", RISCVExtensionVersion{1, 0}}, - - // vendor-defined ('X') extensions - {"xsfvcp", RISCVExtensionVersion{1, 0}}, - {"xtheadba", RISCVExtensionVersion{1, 0}}, - {"xtheadbb", RISCVExtensionVersion{1, 0}}, - {"xtheadbs", RISCVExtensionVersion{1, 0}}, - {"xtheadcmo", RISCVExtensionVersion{1, 0}}, - {"xtheadcondmov", RISCVExtensionVersion{1, 0}}, - {"xtheadfmemidx", RISCVExtensionVersion{1, 0}}, - {"xtheadmac", RISCVExtensionVersion{1, 0}}, - {"xtheadmemidx", RISCVExtensionVersion{1, 0}}, - {"xtheadmempair", RISCVExtensionVersion{1, 0}}, - {"xtheadsync", RISCVExtensionVersion{1, 0}}, - {"xtheadvdot", RISCVExtensionVersion{1, 0}}, - {"xventanacondops", RISCVExtensionVersion{1, 0}}, + {"zvl8192b", RISCVExtensionVersion{1, 0}}, }; +// NOTE: This table should be sorted alphabetically by extension name. static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"smaia", RISCVExtensionVersion{1, 0}}, {"ssaia", RISCVExtensionVersion{1, 0}}, - {"zihintntl", RISCVExtensionVersion{0, 2}}, - {"zfa", RISCVExtensionVersion{0, 2}}, {"zfbfmin", RISCVExtensionVersion{0, 6}}, + {"zicond", RISCVExtensionVersion{1, 0}}, + + {"zihintntl", RISCVExtensionVersion{0, 2}}, + + {"ztso", RISCVExtensionVersion{0, 1}}, + + {"zvbb", RISCVExtensionVersion{0, 9}}, + {"zvbc", RISCVExtensionVersion{0, 9}}, + {"zvfbfmin", RISCVExtensionVersion{0, 6}}, {"zvfbfwma", RISCVExtensionVersion{0, 6}}, {"zvfh", RISCVExtensionVersion{0, 1}}, - {"ztso", RISCVExtensionVersion{0, 1}}, // vector crypto - {"zvbb", RISCVExtensionVersion{0, 9}}, - {"zvbc", RISCVExtensionVersion{0, 9}}, {"zvkg", RISCVExtensionVersion{0, 9}}, {"zvkn", RISCVExtensionVersion{0, 9}}, {"zvknc", RISCVExtensionVersion{0, 9}}, @@ -173,6 +184,19 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"zvkt", RISCVExtensionVersion{0, 9}}, }; +static void verifyTables() { +#ifndef NDEBUG + static std::atomic<bool> TableChecked(false); + if (!TableChecked.load(std::memory_order_relaxed)) { + assert(llvm::is_sorted(SupportedExtensions) && + "Extensions are not sorted by name"); + assert(llvm::is_sorted(SupportedExperimentalExtensions) && + "Experimental extensions are not sorted by name"); + TableChecked.store(true, std::memory_order_relaxed); + } +#endif +} + static bool stripExperimentalPrefix(StringRef &Ext) { return Ext.consume_front("experimental-"); } @@ -273,6 +297,7 @@ bool RISCVISAInfo::isSupportedExtensionFeature(StringRef Ext) { } bool RISCVISAInfo::isSupportedExtension(StringRef Ext) { + verifyTables(); return llvm::any_of(SupportedExtensions, FindByName(Ext)) || llvm::any_of(SupportedExperimentalExtensions, FindByName(Ext)); } _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
