This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6101d720cb49: [RISCV] Relax rules for ordering s/z/x
prefixed extensions in ISA naming strings (authored by asb).
Changed prior to commit:
https://reviews.llvm.org/D149246?vs=517106&id=534930#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D149246/new/
https://reviews.llvm.org/D149246
Files:
clang/docs/ReleaseNotes.rst
clang/test/Driver/riscv-arch.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/unittests/Support/RISCVISAInfoTest.cpp
Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===================================================================
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -192,7 +192,7 @@
EXPECT_EQ(InfoRV64G.getFLen(), 64U);
}
-TEST(ParseArchString, RequiresCanonicalOrderForExtensions) {
+TEST(ParseArchString, RequiresCanonicalOrderForSingleLetterExtensions) {
EXPECT_EQ(
toString(RISCVISAInfo::parseArchString("rv64idf", true).takeError()),
"standard user-level extension not given in canonical order 'f'");
@@ -203,12 +203,10 @@
toString(
RISCVISAInfo::parseArchString("rv32i_zfinx_a", true).takeError()),
"invalid extension prefix 'a'");
- EXPECT_EQ(
- toString(RISCVISAInfo::parseArchString("rv64i_svnapot_zicsr", true)
- .takeError()),
- "standard user-level extension not given in canonical order 'zicsr'");
+ // Canonical ordering not required for z*, s*, and x* extensions.
EXPECT_THAT_EXPECTED(
- RISCVISAInfo::parseArchString("rv64imafdc_zicsr_svnapot", true),
+ RISCVISAInfo::parseArchString(
+ "rv64imafdc_xsfvcp_zicsr_xtheadba_svnapot_zawrs", true),
Succeeded());
}
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -811,9 +811,9 @@
// Parse the ISA string containing non-standard user-level
// extensions, standard supervisor-level extensions and
// non-standard supervisor-level extensions.
- // These extensions start with 'z', 's', 'x' prefixes, follow a
- // canonical order, might have a version number (major, minor)
- // and are separated by a single underscore '_'.
+ // These extensions start with 'z', 's', 'x' prefixes, might have a version
+ // number (major, minor) and are separated by a single underscore '_'. We do
+ // not enforce a canonical order for them.
// Set the hardware features for the extensions that are supported.
// Multi-letter extensions are seperated by a single underscore
@@ -822,9 +822,6 @@
OtherExts.split(Split, '_');
SmallVector<StringRef, 8> AllExts;
- std::array<StringRef, 4> Prefix{"z", "s", "x"};
- auto I = Prefix.begin();
- auto E = Prefix.end();
if (Split.size() > 1 || Split[0] != "") {
for (StringRef Ext : Split) {
if (Ext.empty())
@@ -844,18 +841,6 @@
"invalid extension prefix '" + Ext + "'");
}
- // Check ISA extensions are specified in the canonical order.
- while (I != E && *I != Type)
- ++I;
-
- if (I == E) {
- if (IgnoreUnknown)
- continue;
- return createStringError(errc::invalid_argument,
- "%s not given in canonical order '%s'",
- Desc.str().c_str(), Ext.str().c_str());
- }
-
if (!IgnoreUnknown && Name.size() == Type.size()) {
return createStringError(errc::invalid_argument,
"%s name missing after '%s'",
Index: llvm/docs/RISCVUsage.rst
===================================================================
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -40,6 +40,8 @@
users migrate build systems so as not to rely on this.
* Allowing CSRs to be named without gating on specific extensions. This
applies to all CSR names, not just those in zicsr, zicntr, and zihpm.
+* The ordering of ``z*``, ``s*``, and ``x*`` prefixed extension names is not
+ enforced in user-specified ISA naming strings (e.g. ``-march``).
We are actively deciding not to support multiple specification revisions
at this time. We acknowledge a likely future need, but actively defer the
Index: clang/test/Driver/riscv-arch.c
===================================================================
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -323,8 +323,7 @@
// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
// RV32-X-ORDER: error: invalid arch name 'rv32ixdef_sabc',
-// RV32-X-ORDER: standard supervisor-level extension not given
-// RV32-X-ORDER: in canonical order 'sabc'
+// RV32-X-ORDER unsupported non-standard user-level extension 'xdef'
// RUN: %clang --target=riscv32-unknown-elf -march=rv32ixabc_xabc -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XDUP %s
Index: clang/docs/ReleaseNotes.rst
===================================================================
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -704,6 +704,9 @@
- Added ``attribute(riscv_rvv_vector_bits(__riscv_v_fixed_vlen))`` to allow
the size of a RVV (RISC-V Vector) scalable type to be specified. This allows
RVV scalable vector types to be used in structs or in global variables.
+- The rules for ordering of extensions in ``-march`` strings were relaxed. A
+ canonical ordering is no longer enforced on ``z*``, ``s*``, and ``x*``
+ prefixed extensions.
CUDA/HIP Language Changes
^^^^^^^^^^^^^^^^^^^^^^^^^
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