FreddyYe added inline comments.
================ Comment at: llvm/lib/Target/X86/X86InstrSSE.td:8331 + VR128:$src2, (loadv4i32 addr:$src3), timm:$src4))]>, + Sched<[WriteVecIMul]>; + } ---------------- skan wrote: > Is the schedule appropriate? I referred to SHA1MSG1's, any good ideas? I'll add a FIXME first here. ================ Comment at: llvm/test/MC/Disassembler/X86/sm3-64.txt:4 + +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL ---------------- pengfei wrote: > We can merge 64-bit tests into 32-bit ones. The same below. Due to these instructions support rm form, hard to merge here? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D155147/new/ https://reviews.llvm.org/D155147 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
