craig.topper added inline comments.
================
Comment at:
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c:12
+//
+vint16mf4_t test_vwsll_vv_i16mf4(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+ return __riscv_vwsll_vv_i16mf4(op1, op2, vl);
----------------
craig.topper wrote:
> It doesn't make sense for op2 to be signed. It's a shift amount, its always a
> positive number
The spec doesn't define signed versions of these instrinsics from what I can
see.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D138810/new/
https://reviews.llvm.org/D138810
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