sstwcw added a comment. In D154093#4544496 <https://reviews.llvm.org/D154093#4544496>, @owenpan wrote:
> In D154093#4542339 <https://reviews.llvm.org/D154093#4542339>, @sstwcw wrote: > >> @owenpan What do you think about this revision especially the replacement >> part? > > See D154093#4544495 <https://reviews.llvm.org/D154093#4544495>. Then we can > extend it by using `,` instead of `+` for Verilog (plus inserting a pair of > braces). I added support for that. See the updated description. It turned out that because inserting plus signs may involve inserting parentheses, all the replacement stuff are still needed. So I didn't split the Verilog stuff into a separate patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D154093/new/ https://reviews.llvm.org/D154093 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
