================
@@ -617,24 +617,27 @@ void ASTDeclReader::VisitDecl(Decl *D) {
Reader.getContext());
}
D->setLocation(ThisDeclLoc);
- D->InvalidDecl = Record.readInt();
- if (Record.readInt()) { // hasAttrs
+
+ uint64_t DeclBits = Record.readInt();
+ D->InvalidDecl = DeclBits & 0x1;
+ D->setImplicit(DeclBits & (1 << 2));
+ D->Used = (DeclBits >> 3) & 0x1;
+ IsDeclMarkedUsed |= D->Used;
+ D->setReferenced(DeclBits & (1 << 4));
+ D->setTopLevelDeclInObjCContainer(DeclBits & (1 << 5));
+ D->setAccess((AccessSpecifier)((DeclBits >> 6) & 0x3));
+ D->FromASTFile = true;
+ auto ModuleOwnership = (Decl::ModuleOwnershipKind)((DeclBits >> 8) & 0x7);
----------------
ChuanqiXu9 wrote:
What I had in mind is to introduce a BitPacker, but it can't avoid magic
constants completely. e.g, we have to know that the width of `AccessSpecifier `
should be 2 and the width of `ModuleOwnershipKind` should be 3.
Then we can refactor the above section to:
```
BitPacker Bits = Record.readInt();
D->InvalidDecl = Bits.getNextBit();
D->setImplicit(Bits.getNextBit());
D->Used = Bits.getNextBit();
IsDeclMarkedUsed |= D->Used;
D->setReferenced(Bits.getNextBit());
D->setTopLevelDeclInObjCContainer(Bits.getNextBit());
D->setAccess((AccessSpecifier)Bits.getNextBit</*width = */2>()); // Still we
can't avoid the magic constants completely.
D->FromASTFile = true;
auto ModuleOwnership = (Decl::ModuleOwnershipKind)Bits.getNextBit</*width =
*/3>());
```
Would you be happy about the above form?
https://github.com/llvm/llvm-project/pull/69287
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