github-actions[bot] wrote: <!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code. :warning: <details> <summary> You can test this locally with the following command: </summary> ``````````bash git-clang-format --diff 7aa65c3c5c29658fb38db832771e49251cb16080 0422343f6d7edb9e72da081d85d583fe321c34ec -- clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ld1_single.c clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_loads.c clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_st1_single.c clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_store.c clang/lib/CodeGen/CGBuiltin.cpp llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.h `````````` </details> <details> <summary> View the diff from clang-format here. </summary> ``````````diff diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index d72c9b7ed45f..3d18e00c7973 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -22640,7 +22640,7 @@ static SDValue performScatterStoreCombine(SDNode *N, SelectionDAG &DAG, getScaledOffsetForBitWidth(DAG, Offset, DL, SrcElVT.getSizeInBits()); Opcode = AArch64ISD::SST1Q_PRED; } - + // In the case of non-temporal gather loads there's only one SVE instruction // per data-size: "scalar + vector", i.e. // * stnt1{b|h|w|d} { z0.s }, p0/z, [z0.s, x0] @@ -23600,7 +23600,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N, case Intrinsic::aarch64_sve_ld1q_gather_scalar_offset: return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1Q_MERGE_ZERO); case Intrinsic::aarch64_sve_ld1q_gather_index: - return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1Q_INDEX_MERGE_ZERO); + return performGatherLoadCombine(N, DAG, + AArch64ISD::GLD1Q_INDEX_MERGE_ZERO); case Intrinsic::aarch64_sve_ld1_gather_index: return performGatherLoadCombine(N, DAG, AArch64ISD::GLD1_SCALED_MERGE_ZERO); `````````` </details> https://github.com/llvm/llvm-project/pull/70476 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits