Author: Stefan Pintilie Date: 2023-11-06T12:30:19-05:00 New Revision: 423ad04c67b7fbe7c6a6b4e0591bff40844c6027
URL: https://github.com/llvm/llvm-project/commit/423ad04c67b7fbe7c6a6b4e0591bff40844c6027 DIFF: https://github.com/llvm/llvm-project/commit/423ad04c67b7fbe7c6a6b4e0591bff40844c6027.diff LOG: [PowerPC] Add an alias for -mregnames so that full register names used in assembly. (#70255) This option already exists on GCC and so it is being added to LLVM so that we use the same option as them. Added: clang/test/CodeGen/PowerPC/ppc-full-reg-names.c Modified: clang/include/clang/Basic/CodeGenOptions.def clang/include/clang/Driver/Options.td clang/lib/CodeGen/BackendUtil.cpp clang/lib/Driver/ToolChains/Clang.cpp llvm/include/llvm/MC/MCAsmInfo.h llvm/include/llvm/MC/MCTargetOptions.h llvm/lib/CodeGen/LLVMTargetMachine.cpp llvm/lib/MC/MCAsmInfo.cpp llvm/lib/MC/MCTargetOptions.cpp llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp Removed: ################################################################################ diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def index d7588fd430764cb..843559f202abe35 100644 --- a/clang/include/clang/Basic/CodeGenOptions.def +++ b/clang/include/clang/Basic/CodeGenOptions.def @@ -197,6 +197,7 @@ CODEGENOPT(HIPCorrectlyRoundedDivSqrt, 1, 1) ///< -fno-hip-fp32-correctly-rounde CODEGENOPT(HIPSaveKernelArgName, 1, 0) ///< Set when -fhip-kernel-arg-name is enabled. CODEGENOPT(UniqueInternalLinkageNames, 1, 0) ///< Internal Linkage symbols get unique names. CODEGENOPT(SplitMachineFunctions, 1, 0) ///< Split machine functions using profile information. +CODEGENOPT(PPCUseFullRegisterNames, 1, 0) ///< Print full register names in assembly /// When false, this attempts to generate code as if the result of an /// overflowing conversion matches the overflowing behavior of a target's native diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 009ac1cfd8dc1b4..5219f90650d07c6 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -4789,6 +4789,12 @@ def mrop_protect : Flag<["-"], "mrop-protect">, Group<m_ppc_Features_Group>; def mprivileged : Flag<["-"], "mprivileged">, Group<m_ppc_Features_Group>; + +defm regnames : BoolOption<"m", "regnames", + CodeGenOpts<"PPCUseFullRegisterNames">, DefaultFalse, + PosFlag<SetTrue, [], [ClangOption, CC1Option], "Use full register names when writing assembly output">, + NegFlag<SetFalse, [], [ClangOption], "Use only register numbers when writing assembly output">>, + Group<m_Group>; } // let Flags = [TargetSpecific] def maix_small_local_exec_tls : Flag<["-"], "maix-small-local-exec-tls">, Group<m_ppc_Features_Group>, diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp index 70accce456d3c07..06bd0ad059835cf 100644 --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -488,6 +488,8 @@ static bool initTargetOptions(DiagnosticsEngine &Diags, Options.MCOptions.Argv0 = CodeGenOpts.Argv0; Options.MCOptions.CommandLineArgs = CodeGenOpts.CommandLineArgs; Options.MCOptions.AsSecureLogFile = CodeGenOpts.AsSecureLogFile; + Options.MCOptions.PPCUseFullRegisterNames = + CodeGenOpts.PPCUseFullRegisterNames; Options.MisExpect = CodeGenOpts.MisExpect; return true; diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 3e2c13069612876..22f992166ded6c0 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -5014,6 +5014,10 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.AddLastArg(CmdArgs, options::OPT_fthinlto_index_EQ); } + if (Triple.isPPC()) + Args.addOptInFlag(CmdArgs, options::OPT_mregnames, + options::OPT_mno_regnames); + if (Args.getLastArg(options::OPT_fthin_link_bitcode_EQ)) Args.AddLastArg(CmdArgs, options::OPT_fthin_link_bitcode_EQ); diff --git a/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c b/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c new file mode 100644 index 000000000000000..70ed14dbc32c6b8 --- /dev/null +++ b/clang/test/CodeGen/PowerPC/ppc-full-reg-names.c @@ -0,0 +1,8 @@ +// REQUIRES: powerpc-registered-target +// RUN: %clang -### -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mregnames \ +// RUN: %s 2>&1 >/dev/null | FileCheck %s --check-prefix=FULLNAMES +// RUN: %clang -### -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mno-regnames \ +// RUN: %s 2>&1 >/dev/null | FileCheck %s --check-prefix=NOFULLNAMES + +// FULLNAMES: -mregnames +// NOFULLNAMES-NOT: -mregnames diff --git a/llvm/include/llvm/MC/MCAsmInfo.h b/llvm/include/llvm/MC/MCAsmInfo.h index c28cd12112358c7..a3c9b19e859d938 100644 --- a/llvm/include/llvm/MC/MCAsmInfo.h +++ b/llvm/include/llvm/MC/MCAsmInfo.h @@ -240,6 +240,9 @@ class MCAsmInfo { /// True if the target supports LEB128 directives. bool HasLEB128Directives = true; + /// True if full register names are printed. + bool PPCUseFullRegisterNames = false; + //===--- Data Emission Directives -------------------------------------===// /// This should be set to the directive used to get some number of zero (and @@ -710,6 +713,9 @@ class MCAsmInfo { bool hasLEB128Directives() const { return HasLEB128Directives; } + bool useFullRegisterNames() const { return PPCUseFullRegisterNames; } + void setFullRegisterNames(bool V) { PPCUseFullRegisterNames = V; } + const char *getZeroDirective() const { return ZeroDirective; } bool doesZeroDirectiveSupportNonZeroValue() const { return ZeroDirectiveSupportsNonZeroValue; diff --git a/llvm/include/llvm/MC/MCTargetOptions.h b/llvm/include/llvm/MC/MCTargetOptions.h index 9fc1e07d085ebaa..afb329eb6f935ec 100644 --- a/llvm/include/llvm/MC/MCTargetOptions.h +++ b/llvm/include/llvm/MC/MCTargetOptions.h @@ -89,6 +89,9 @@ class MCTargetOptions { // functions on Darwins. bool EmitCompactUnwindNonCanonical : 1; + // Whether or not to use full register names on PowerPC. + bool PPCUseFullRegisterNames : 1; + MCTargetOptions(); /// getABIName - If this returns a non-empty string this represents the diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp index 87a17b88db12433..42cabb58e5189d5 100644 --- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp +++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp @@ -81,6 +81,8 @@ void LLVMTargetMachine::initAsmInfo() { TmpAsmInfo->setRelaxELFRelocations(Options.RelaxELFRelocations); + TmpAsmInfo->setFullRegisterNames(Options.MCOptions.PPCUseFullRegisterNames); + if (Options.ExceptionModel != ExceptionHandling::None) TmpAsmInfo->setExceptionsType(Options.ExceptionModel); diff --git a/llvm/lib/MC/MCAsmInfo.cpp b/llvm/lib/MC/MCAsmInfo.cpp index 1675e24301dc69c..290be40371663fb 100644 --- a/llvm/lib/MC/MCAsmInfo.cpp +++ b/llvm/lib/MC/MCAsmInfo.cpp @@ -67,6 +67,7 @@ MCAsmInfo::MCAsmInfo() { UseIntegratedAssembler = true; ParseInlineAsmUsingAsmParser = false; PreserveAsmComments = true; + PPCUseFullRegisterNames = false; } MCAsmInfo::~MCAsmInfo() = default; diff --git a/llvm/lib/MC/MCTargetOptions.cpp b/llvm/lib/MC/MCTargetOptions.cpp index 8fea8c7715bdc81..07c6e752cb613d0 100644 --- a/llvm/lib/MC/MCTargetOptions.cpp +++ b/llvm/lib/MC/MCTargetOptions.cpp @@ -19,7 +19,7 @@ MCTargetOptions::MCTargetOptions() PreserveAsmComments(true), Dwarf64(false), EmitDwarfUnwind(EmitDwarfUnwindType::Default), MCUseDwarfDirectory(DefaultDwarfDirectory), - EmitCompactUnwindNonCanonical(false) {} + EmitCompactUnwindNonCanonical(false), PPCUseFullRegisterNames(false) {} StringRef MCTargetOptions::getABIName() const { return ABIName; diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp index 0ee7f9f49843172..ccbb650c65365b4 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp @@ -13,6 +13,7 @@ #include "MCTargetDesc/PPCInstPrinter.h" #include "MCTargetDesc/PPCMCTargetDesc.h" #include "MCTargetDesc/PPCPredicates.h" +#include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" @@ -596,7 +597,8 @@ void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo, /// showRegistersWithPercentPrefix - Check if this register name should be /// printed with a percentage symbol as prefix. bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const { - if (!FullRegNamesWithPercent || TT.getOS() == Triple::AIX) + if ((!FullRegNamesWithPercent && !MAI.useFullRegisterNames()) || + TT.getOS() == Triple::AIX) return false; switch (RegName[0]) { @@ -613,10 +615,10 @@ bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const { /// getVerboseConditionalRegName - This method expands the condition register /// when requested explicitly or targetting Darwin. -const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum, - unsigned RegEncoding) - const { - if (!FullRegNames) +const char * +PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum, + unsigned RegEncoding) const { + if (!FullRegNames && !MAI.useFullRegisterNames()) return nullptr; if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN) return nullptr; @@ -636,7 +638,7 @@ const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum, // showRegistersWithPrefix - This method determines whether registers // should be number-only or include the prefix. bool PPCInstPrinter::showRegistersWithPrefix() const { - return FullRegNamesWithPercent || FullRegNames; + return FullRegNamesWithPercent || FullRegNames || MAI.useFullRegisterNames(); } void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
