https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/71953
>From cb6e6b5c6fe76a2b4a3bd1d78f4f7cec82d84067 Mon Sep 17 00:00:00 2001
From: Matt Devereau <matthew.dever...@arm.com>
Date: Fri, 10 Nov 2023 13:40:31 +0000
Subject: [PATCH 1/3] Add SME2 builtins for pfalse and ptrue
Extend pfalse and ptrue builtins with svcount_t return types
to be enabled for sve2p1 and sme2
---
clang/include/clang/Basic/arm_sve.td | 23 +++----------
clang/lib/Sema/Sema.cpp | 3 +-
.../acle_sme2_ptrue_pfalse_attr.c | 34 +++++++++++++++++++
3 files changed, 41 insertions(+), 19 deletions(-)
create mode 100644
clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
diff --git a/clang/include/clang/Basic/arm_sve.td
b/clang/include/clang/Basic/arm_sve.td
index 3f69a3df9e616..44a8a2328081b 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -1925,8 +1925,6 @@ def SVBGRP_N : SInst<"svbgrp[_n_{d}]", "dda", "UcUsUiUl",
MergeNone, "aarch64_sv
let TargetGuard = "sve2p1" in {
def SVFCLAMP : SInst<"svclamp[_{d}]", "dddd", "hfd", MergeNone,
"aarch64_sve_fclamp", [], []>;
-def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone,
"aarch64_sve_ptrue_{d}", [IsOverloadNone], []>;
-def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "",
[IsOverloadNone]>;
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [], [ImmCheck<1, ImmCheck0_3>]>;
def SVPEXT_X2 : SInst<"svpext_lane_{d}_x2", "2.P}i", "QcQsQiQl",
MergeNone, "aarch64_sve_pext_x2", [], [ImmCheck<1, ImmCheck0_1>]>;
@@ -2045,23 +2043,12 @@ def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i",
"QcQsQiQl", MergeNone, "aarch64_sv
defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl", "aarch64_sve_revd">;
}
+let TargetGuard = "sve2p1|sme2" in {
+ def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone,
"aarch64_sve_ptrue_{d}", [IsOverloadNone], []>;
+ def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "",
[IsOverloadNone]>;
+}
-let TargetGuard = "sve2p1,b16b16" in {
-defm SVMUL_BF : SInstZPZZ<"svmul", "b", "aarch64_sve_fmul",
"aarch64_sve_fmul_u">;
-defm SVADD_BF : SInstZPZZ<"svadd", "b", "aarch64_sve_fadd",
"aarch64_sve_fadd_u">;
-defm SVSUB_BF : SInstZPZZ<"svsub", "b", "aarch64_sve_fsub",
"aarch64_sve_fsub_u">;
-defm SVMAXNM_BF : SInstZPZZ<"svmaxnm","b", "aarch64_sve_fmaxnm",
"aarch64_sve_fmaxnm_u">;
-defm SVMINNM_BF : SInstZPZZ<"svminnm","b", "aarch64_sve_fminnm",
"aarch64_sve_fminnm_u">;
-defm SVMAX_BF : SInstZPZZ<"svmax", "b", "aarch64_sve_fmax",
"aarch64_sve_fmax_u">;
-defm SVMIN_BF : SInstZPZZ<"svmin", "b", "aarch64_sve_fmin",
"aarch64_sve_fmin_u">;
-defm SVMLA_BF : SInstZPZZZ<"svmla", "b", "aarch64_sve_fmla",
"aarch64_sve_fmla_u", []>;
-defm SVMLS_BF : SInstZPZZZ<"svmls", "b", "aarch64_sve_fmls",
"aarch64_sve_fmls_u", []>;
-def SVMLA_LANE_BF : SInst<"svmla_lane[_{d}]", "ddddi", "b", MergeNone,
"aarch64_sve_fmla_lane", [], [ImmCheck<3, ImmCheckLaneIndex, 2>]>;
-def SVMLS_LANE_BF : SInst<"svmls_lane[_{d}]", "ddddi", "b", MergeNone,
"aarch64_sve_fmls_lane", [], [ImmCheck<3, ImmCheckLaneIndex, 2>]>;
-def SVMUL_LANE_BF : SInst<"svmul_lane[_{d}]", "dddi", "b", MergeNone,
"aarch64_sve_fmul_lane", [], [ImmCheck<2, ImmCheckLaneIndex, 1>]>;
-def SVFCLAMP_BF : SInst<"svclamp[_{d}]", "dddd", "b", MergeNone,
"aarch64_sve_fclamp", [], []>;
-} //sve2p1,b16b16
-
+////////////////////////////////////////////////////////////////////////////////
// SME2
// SME intrinsics which operate only on vectors and do not require ZA should
be added here,
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index 9771aaa2f3b03..b9187cf86ebf7 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2085,7 +2085,8 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
llvm::StringMap<bool> CallerFeatureMap;
Context.getFunctionFeatureMap(CallerFeatureMap, FD);
if (!Builtin::evaluateRequiredTargetFeatures(
- "sve", CallerFeatureMap))
+ "sve", CallerFeatureMap) && !Builtin::evaluateRequiredTargetFeatures(
+ "sme", CallerFeatureMap))
Diag(D->getLocation(), diag::err_sve_vector_in_non_sve_target) << Ty;
}
};
diff --git
a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
new file mode 100644
index 0000000000000..90d9434d87cf4
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
@@ -0,0 +1,34 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -o /dev/null %s
+#include <arm_sve.h>
+
+// CHECK-LABEL: @test_svptrue_c8_attr(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.ptrue.c8()
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z20test_svptrue_c8_attrv(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.ptrue.c8()
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svptrue_c8_attr(void) __arm_streaming {
+ return svptrue_c8();
+}
+
+// CHECK-LABEL: @test_svptrue_c(
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1>
zeroinitializer)
+// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+// CPP-CHECK-LABEL: @_Z14test_svptrue_cv(
+// CPP-CHECK-NEXT: entry:
+// CPP-CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1>
zeroinitializer)
+// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
+//
+svcount_t test_svptrue_c(void) __arm_streaming {
+ return svpfalse_c();
+}
>From 78f60b72ad3d98e825db6963cb70ceeb79a4a09a Mon Sep 17 00:00:00 2001
From: Matt Devereau <matthew.dever...@arm.com>
Date: Wed, 15 Nov 2023 11:24:13 +0000
Subject: [PATCH 2/3] Update test
---
clang/include/clang/Basic/arm_sve.td | 4 ++--
.../aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c | 7 ++++---
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/clang/include/clang/Basic/arm_sve.td
b/clang/include/clang/Basic/arm_sve.td
index 44a8a2328081b..1106f3e612273 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2044,8 +2044,8 @@ defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl",
"aarch64_sve_revd">;
}
let TargetGuard = "sve2p1|sme2" in {
- def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone,
"aarch64_sve_ptrue_{d}", [IsOverloadNone], []>;
- def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "",
[IsOverloadNone]>;
+ def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone,
"aarch64_sve_ptrue_{d}", [IsOverloadNone, IsStreaming], []>;
+ def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "",
[IsOverloadNone, IsStreamingCompatible]>;
}
////////////////////////////////////////////////////////////////////////////////
diff --git
a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
index 90d9434d87cf4..7d2d70bc38672 100644
--- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
+++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
@@ -19,16 +19,17 @@ svcount_t test_svptrue_c8_attr(void) __arm_streaming {
return svptrue_c8();
}
-// CHECK-LABEL: @test_svptrue_c(
+// CHECK-LABEL: @test_svpfalse_c_attr(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1>
zeroinitializer)
// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
//
-// CPP-CHECK-LABEL: @_Z14test_svptrue_cv(
+// CPP-CHECK-LABEL: @_Z20test_svpfalse_c_attrv(
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1>
zeroinitializer)
// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
//
-svcount_t test_svptrue_c(void) __arm_streaming {
+svcount_t test_svpfalse_c_attr(void) __arm_streaming_compatible
+{
return svpfalse_c();
}
>From 768f316d9514c8785784e17cbe0b84613af714cc Mon Sep 17 00:00:00 2001
From: Matt Devereau <matthew.dever...@arm.com>
Date: Wed, 6 Dec 2023 15:17:59 +0000
Subject: [PATCH 3/3] Update SVPTRUE_COUNT to use IsStreamingCompatible, delete
new file added
---
clang/include/clang/Basic/arm_sve.td | 21 +++++++++--
clang/lib/Sema/Sema.cpp | 5 ++-
.../acle_sme2_ptrue_pfalse_attr.c | 35 -------------------
.../acle_sve2p1_pfalse.c | 17 ++++-----
.../acle_sve2p1_ptrue.c | 10 +++---
5 files changed, 33 insertions(+), 55 deletions(-)
delete mode 100644
clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
diff --git a/clang/include/clang/Basic/arm_sve.td
b/clang/include/clang/Basic/arm_sve.td
index 1106f3e612273..317e5c1ccb261 100644
--- a/clang/include/clang/Basic/arm_sve.td
+++ b/clang/include/clang/Basic/arm_sve.td
@@ -2044,11 +2044,28 @@ defm SVREVD : SInstZPZ<"svrevd", "csilUcUsUiUl",
"aarch64_sve_revd">;
}
let TargetGuard = "sve2p1|sme2" in {
- def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone,
"aarch64_sve_ptrue_{d}", [IsOverloadNone, IsStreaming], []>;
+ //FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when
available
+ def SVPTRUE_COUNT : SInst<"svptrue_{d}", "}v", "QcQsQiQl", MergeNone,
"aarch64_sve_ptrue_{d}", [IsOverloadNone, IsStreamingCompatible], []>;
+
def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "",
[IsOverloadNone, IsStreamingCompatible]>;
}
-////////////////////////////////////////////////////////////////////////////////
+let TargetGuard = "sve2p1,b16b16" in {
+defm SVMUL_BF : SInstZPZZ<"svmul", "b", "aarch64_sve_fmul",
"aarch64_sve_fmul_u">;
+defm SVADD_BF : SInstZPZZ<"svadd", "b", "aarch64_sve_fadd",
"aarch64_sve_fadd_u">;
+defm SVSUB_BF : SInstZPZZ<"svsub", "b", "aarch64_sve_fsub",
"aarch64_sve_fsub_u">;
+defm SVMAXNM_BF : SInstZPZZ<"svmaxnm","b", "aarch64_sve_fmaxnm",
"aarch64_sve_fmaxnm_u">;
+defm SVMINNM_BF : SInstZPZZ<"svminnm","b", "aarch64_sve_fminnm",
"aarch64_sve_fminnm_u">;
+defm SVMAX_BF : SInstZPZZ<"svmax", "b", "aarch64_sve_fmax",
"aarch64_sve_fmax_u">;
+defm SVMIN_BF : SInstZPZZ<"svmin", "b", "aarch64_sve_fmin",
"aarch64_sve_fmin_u">;
+defm SVMLA_BF : SInstZPZZZ<"svmla", "b", "aarch64_sve_fmla",
"aarch64_sve_fmla_u", []>;
+defm SVMLS_BF : SInstZPZZZ<"svmls", "b", "aarch64_sve_fmls",
"aarch64_sve_fmls_u", []>;
+def SVMLA_LANE_BF : SInst<"svmla_lane[_{d}]", "ddddi", "b", MergeNone,
"aarch64_sve_fmla_lane", [], [ImmCheck<3, ImmCheckLaneIndex, 2>]>;
+def SVMLS_LANE_BF : SInst<"svmls_lane[_{d}]", "ddddi", "b", MergeNone,
"aarch64_sve_fmls_lane", [], [ImmCheck<3, ImmCheckLaneIndex, 2>]>;
+def SVMUL_LANE_BF : SInst<"svmul_lane[_{d}]", "dddi", "b", MergeNone,
"aarch64_sve_fmul_lane", [], [ImmCheck<2, ImmCheckLaneIndex, 1>]>;
+def SVFCLAMP_BF : SInst<"svclamp[_{d}]", "dddd", "b", MergeNone,
"aarch64_sve_fclamp", [], []>;
+} //sve2p1,b16b16
+
// SME2
// SME intrinsics which operate only on vectors and do not require ZA should
be added here,
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index b9187cf86ebf7..2c7ecf4610de0 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2084,9 +2084,8 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
llvm::StringMap<bool> CallerFeatureMap;
Context.getFunctionFeatureMap(CallerFeatureMap, FD);
- if (!Builtin::evaluateRequiredTargetFeatures(
- "sve", CallerFeatureMap) && !Builtin::evaluateRequiredTargetFeatures(
- "sme", CallerFeatureMap))
+ if (!Builtin::evaluateRequiredTargetFeatures("sve", CallerFeatureMap) &&
+ !Builtin::evaluateRequiredTargetFeatures("sme", CallerFeatureMap))
Diag(D->getLocation(), diag::err_sve_vector_in_non_sve_target) << Ty;
}
};
diff --git
a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
deleted file mode 100644
index 7d2d70bc38672..0000000000000
--- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_ptrue_pfalse_attr.c
+++ /dev/null
@@ -1,35 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s
-check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -o /dev/null %s
-#include <arm_sve.h>
-
-// CHECK-LABEL: @test_svptrue_c8_attr(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.ptrue.c8()
-// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z20test_svptrue_c8_attrv(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.ptrue.c8()
-// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
-//
-svcount_t test_svptrue_c8_attr(void) __arm_streaming {
- return svptrue_c8();
-}
-
-// CHECK-LABEL: @test_svpfalse_c_attr(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1>
zeroinitializer)
-// CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z20test_svpfalse_c_attrv(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = call target("aarch64.svcount")
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1>
zeroinitializer)
-// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
-//
-svcount_t test_svpfalse_c_attr(void) __arm_streaming_compatible
-{
- return svpfalse_c();
-}
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pfalse.c
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pfalse.c
index 5432862dcf527..19993e5418128 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pfalse.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_pfalse.c
@@ -1,18 +1,13 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S
-passes=mem2reg,tailcallelim | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S
-passes=mem2reg,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S
-passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s
| opt -S -passes=mem2reg,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu
-target-feature +sve2p1 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x
c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
-check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S
-passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-disable-O0-optnone -Werror -Wall -o /dev/null %s
-#include <arm_sve.h>
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S
-disable-O0-optnone -Werror -Wall -o /dev/null %s
-#ifdef SVE_OVERLOADED_FORMS
-// A simple used,unused... macro, long enough to represent any SVE builtin.
-#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
-#else
-#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
-#endif
+#include <arm_sve.h>
// CHECK-LABEL: @test_svpfalse_c(
// CHECK-NEXT: entry:
@@ -24,7 +19,7 @@
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount")
@llvm.aarch64.sve.convert.from.svbool.taarch64.svcountt(<vscale x 16 x i1>
zeroinitializer)
// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
//
-svcount_t test_svpfalse_c()
+svcount_t test_svpfalse_c(void) __arm_streaming_compatible
{
- return SVE_ACLE_FUNC(svpfalse_c,,,)();
+ return svpfalse_c();
}
diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c
b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c
index c8fd843500560..bc8fee873ac39 100644
--- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c
+++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_ptrue.c
@@ -1,7 +1,9 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -O1
-Werror -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -O1
-Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK
#include <arm_sve.h>
@@ -15,7 +17,7 @@
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount")
@llvm.aarch64.sve.ptrue.c8()
// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
//
-svcount_t test_svptrue_c8(void) {
+svcount_t test_svptrue_c8(void) __arm_streaming_compatible {
return svptrue_c8();
}
@@ -29,7 +31,7 @@ svcount_t test_svptrue_c8(void) {
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount")
@llvm.aarch64.sve.ptrue.c16()
// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
//
-svcount_t test_svptrue_c16(void) {
+svcount_t test_svptrue_c16(void) __arm_streaming_compatible {
return svptrue_c16();
}
@@ -43,7 +45,7 @@ svcount_t test_svptrue_c16(void) {
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount")
@llvm.aarch64.sve.ptrue.c32()
// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
//
-svcount_t test_svptrue_c32(void) {
+svcount_t test_svptrue_c32(void) __arm_streaming_compatible {
return svptrue_c32();
}
@@ -57,6 +59,6 @@ svcount_t test_svptrue_c32(void) {
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call target("aarch64.svcount")
@llvm.aarch64.sve.ptrue.c64()
// CPP-CHECK-NEXT: ret target("aarch64.svcount") [[TMP0]]
//
-svcount_t test_svptrue_c64(void) {
+svcount_t test_svptrue_c64(void) __arm_streaming_compatible {
return svptrue_c64();
}
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