github-actions[bot] wrote: <!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code. :warning: <details> <summary> You can test this locally with the following command: </summary> ``````````bash git-clang-format --diff 7388b7422f9307dd5ae3fe3876a676d83d702daf 3e000d49ecc3769efa2051332c04163b84b0f9ae -- clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c clang/test/CodeGen/RISCV/riscv-vector-callingconv.cpp clang/include/clang/Basic/Specifiers.h clang/lib/AST/ItaniumMangle.cpp clang/lib/AST/Type.cpp clang/lib/AST/TypePrinter.cpp clang/lib/Basic/Targets/RISCV.cpp clang/lib/Basic/Targets/RISCV.h clang/lib/CodeGen/CGCall.cpp clang/lib/Sema/SemaDeclAttr.cpp clang/lib/Sema/SemaType.cpp llvm/include/llvm/AsmParser/LLToken.h llvm/include/llvm/IR/CallingConv.h llvm/lib/AsmParser/LLLexer.cpp llvm/lib/AsmParser/LLParser.cpp llvm/lib/IR/AsmWriter.cpp llvm/lib/Target/RISCV/RISCVFrameLowering.cpp llvm/lib/Target/RISCV/RISCVFrameLowering.h llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp `````````` </details> <details> <summary> View the diff from clang-format here. </summary> ``````````diff diff --git a/clang/include/clang/Basic/Specifiers.h b/clang/include/clang/Basic/Specifiers.h index 72a10e25c9..412874e1c2 100644 --- a/clang/include/clang/Basic/Specifiers.h +++ b/clang/include/clang/Basic/Specifiers.h @@ -271,29 +271,29 @@ namespace clang { /// CallingConv - Specifies the calling convention that a function uses. enum CallingConv { - CC_C, // __attribute__((cdecl)) - CC_X86StdCall, // __attribute__((stdcall)) - CC_X86FastCall, // __attribute__((fastcall)) - CC_X86ThisCall, // __attribute__((thiscall)) - CC_X86VectorCall, // __attribute__((vectorcall)) - CC_X86Pascal, // __attribute__((pascal)) - CC_Win64, // __attribute__((ms_abi)) - CC_X86_64SysV, // __attribute__((sysv_abi)) - CC_X86RegCall, // __attribute__((regcall)) - CC_AAPCS, // __attribute__((pcs("aapcs"))) - CC_AAPCS_VFP, // __attribute__((pcs("aapcs-vfp"))) - CC_IntelOclBicc, // __attribute__((intel_ocl_bicc)) - CC_SpirFunction, // default for OpenCL functions on SPIR target - CC_OpenCLKernel, // inferred for OpenCL kernels - CC_Swift, // __attribute__((swiftcall)) + CC_C, // __attribute__((cdecl)) + CC_X86StdCall, // __attribute__((stdcall)) + CC_X86FastCall, // __attribute__((fastcall)) + CC_X86ThisCall, // __attribute__((thiscall)) + CC_X86VectorCall, // __attribute__((vectorcall)) + CC_X86Pascal, // __attribute__((pascal)) + CC_Win64, // __attribute__((ms_abi)) + CC_X86_64SysV, // __attribute__((sysv_abi)) + CC_X86RegCall, // __attribute__((regcall)) + CC_AAPCS, // __attribute__((pcs("aapcs"))) + CC_AAPCS_VFP, // __attribute__((pcs("aapcs-vfp"))) + CC_IntelOclBicc, // __attribute__((intel_ocl_bicc)) + CC_SpirFunction, // default for OpenCL functions on SPIR target + CC_OpenCLKernel, // inferred for OpenCL kernels + CC_Swift, // __attribute__((swiftcall)) CC_SwiftAsync, // __attribute__((swiftasynccall)) - CC_PreserveMost, // __attribute__((preserve_most)) - CC_PreserveAll, // __attribute__((preserve_all)) + CC_PreserveMost, // __attribute__((preserve_most)) + CC_PreserveAll, // __attribute__((preserve_all)) CC_AArch64VectorCall, // __attribute__((aarch64_vector_pcs)) - CC_AArch64SVEPCS, // __attribute__((aarch64_sve_pcs)) - CC_AMDGPUKernelCall, // __attribute__((amdgpu_kernel)) - CC_M68kRTD, // __attribute__((m68k_rtd)) - CC_RISCVVectorCall, // __attribute__((riscv_vector_cc)) + CC_AArch64SVEPCS, // __attribute__((aarch64_sve_pcs)) + CC_AMDGPUKernelCall, // __attribute__((amdgpu_kernel)) + CC_M68kRTD, // __attribute__((m68k_rtd)) + CC_RISCVVectorCall, // __attribute__((riscv_vector_cc)) }; /// Checks whether the given calling convention supports variadic diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp index 8895a1065d..01c4adf9ca 100644 --- a/clang/lib/AST/Type.cpp +++ b/clang/lib/AST/Type.cpp @@ -3409,7 +3409,8 @@ StringRef FunctionType::getNameForCallConv(CallingConv CC) { case CC_PreserveMost: return "preserve_most"; case CC_PreserveAll: return "preserve_all"; case CC_M68kRTD: return "m68k_rtd"; - case CC_RISCVVectorCall: return "riscv_vector_cc"; + case CC_RISCVVectorCall: + return "riscv_vector_cc"; } llvm_unreachable("Invalid calling convention."); diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index 0a5cf09040..bc54216a5e 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -484,10 +484,10 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const { TargetInfo::CallingConvCheckResult RISCVTargetInfo::checkCallingConvention(CallingConv CC) const { switch (CC) { - default: - return CCCR_Warning; - case CC_C: - case CC_RISCVVectorCall: - return CCCR_OK; + default: + return CCCR_Warning; + case CC_C: + case CC_RISCVVectorCall: + return CCCR_OK; } } diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index a099bb0efd..d10709b907 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -73,7 +73,8 @@ unsigned CodeGenTypes::ClangCallConvToLLVMCallConv(CallingConv CC) { case CC_Swift: return llvm::CallingConv::Swift; case CC_SwiftAsync: return llvm::CallingConv::SwiftTail; case CC_M68kRTD: return llvm::CallingConv::M68k_RTD; - case CC_RISCVVectorCall: return llvm::CallingConv::RISCV_VectorCall; + case CC_RISCVVectorCall: + return llvm::CallingConv::RISCV_VectorCall; } } diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp index bcdbb75abd..16a10a5529 100644 --- a/llvm/lib/AsmParser/LLParser.cpp +++ b/llvm/lib/AsmParser/LLParser.cpp @@ -2075,7 +2075,9 @@ bool LLParser::parseOptionalCallingConv(unsigned &CC) { case lltok::kw_tailcc: CC = CallingConv::Tail; break; case lltok::kw_m68k_rtdcc: CC = CallingConv::M68k_RTD; break; case lltok::kw_graalcc: CC = CallingConv::GRAAL; break; - case lltok::kw_riscv_vector_cc:CC = CallingConv::RISCV_VectorCall; break; + case lltok::kw_riscv_vector_cc: + CC = CallingConv::RISCV_VectorCall; + break; case lltok::kw_cc: { Lex.Lex(); return parseUInt32(CC); diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index 119092e5c6..93e7b98320 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -362,7 +362,9 @@ static void PrintCallingConv(unsigned cc, raw_ostream &Out) { case CallingConv::AMDGPU_KERNEL: Out << "amdgpu_kernel"; break; case CallingConv::AMDGPU_Gfx: Out << "amdgpu_gfx"; break; case CallingConv::M68k_RTD: Out << "m68k_rtdcc"; break; - case CallingConv::RISCV_VectorCall: Out << "riscv_vector_cc"; break; + case CallingConv::RISCV_VectorCall: + Out << "riscv_vector_cc"; + break; } } diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index ae51dbdb92..e75c9cbe71 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -455,9 +455,9 @@ static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI, else Comment << printReg(Reg, &TRI); - appendScalableVectorExpression( - Expr, FixedOffset, ScalableOffset, - TRI.getDwarfRegNum(RISCV::VLENB, true), Comment); + appendScalableVectorExpression(Expr, FixedOffset, ScalableOffset, + TRI.getDwarfRegNum(RISCV::VLENB, true), + Comment); SmallString<64> DefCfaExpr; uint8_t buffer[16]; @@ -470,8 +470,7 @@ static MCCFIInstruction createDefCFAExpression(const TargetRegisterInfo &TRI, } static MCCFIInstruction createDefCFAOffset(const TargetRegisterInfo &TRI, - Register Reg, - uint64_t FixedOffset, + Register Reg, uint64_t FixedOffset, uint64_t ScalableOffset) { assert(ScalableOffset != 0 && "Did not need to adjust CFA for RVV"); SmallString<64> Expr; @@ -480,9 +479,9 @@ static MCCFIInstruction createDefCFAOffset(const TargetRegisterInfo &TRI, Comment << printReg(Reg, &TRI) << " @ cfa"; // Build up the expression (FixedOffset + ScalableOffset * VLENB). - appendScalableVectorExpression( - Expr, FixedOffset, ScalableOffset, - TRI.getDwarfRegNum(RISCV::VLENB, true), Comment); + appendScalableVectorExpression(Expr, FixedOffset, ScalableOffset, + TRI.getDwarfRegNum(RISCV::VLENB, true), + Comment); SmallString<64> DefCfaExpr; uint8_t buffer[16]; @@ -615,7 +614,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF, // directives. for (const auto &Entry : CSI) { int FrameIdx = Entry.getFrameIdx(); - if (FrameIdx >=0 && + if (FrameIdx >= 0 && MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector) continue; @@ -1470,12 +1469,12 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters( const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, CSI); auto storeRegToStackSlot = [&](decltype(UnmanagedCSI) CSInfo) { - for (auto &CS: CSInfo) { + for (auto &CS : CSInfo) { // Insert the spill to the stack frame. Register Reg = CS.getReg(); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), CS.getFrameIdx(), - RC, TRI, Register()); + TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), + CS.getFrameIdx(), RC, TRI, Register()); } }; storeRegToStackSlot(UnmanagedCSI); @@ -1497,8 +1496,7 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI( return; uint64_t FixedSize = getStackSizeWithRVVPadding(*MF) + - RVFI->getLibCallStackSize() + - RVFI->getRVPushStackSize(); + RVFI->getLibCallStackSize() + RVFI->getRVPushStackSize(); if (!HasFP) { uint64_t ScalarLocalVarSize = MFI.getStackSize() - RVFI->getCalleeSavedStackSize() - @@ -1507,13 +1505,13 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI( FixedSize -= ScalarLocalVarSize; } - for (auto &CS: RVVCSI) { + for (auto &CS : RVVCSI) { // Insert the spill to the stack frame. int FI = CS.getFrameIdx(); if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::ScalableVector) { - unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset( - *STI.getRegisterInfo(), CS.getReg(), - -FixedSize, MFI.getObjectOffset(FI) / 8)); + unsigned CFIIndex = MF->addFrameInst( + createDefCFAOffset(*STI.getRegisterInfo(), CS.getReg(), -FixedSize, + MFI.getObjectOffset(FI) / 8)); BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex) .setMIFlag(MachineInstr::FrameSetup); @@ -1590,12 +1588,13 @@ bool RISCVFrameLowering::restoreCalleeSavedRegisters( const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, CSI); auto loadRegFromStackSlot = [&](decltype(UnmanagedCSI) CSInfo) { - for (auto &CS: CSInfo) { + for (auto &CS : CSInfo) { Register Reg = CS.getReg(); const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI, Register()); - assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!"); + assert(MI != MBB.begin() && + "loadRegFromStackSlot didn't insert any code!"); } }; loadRegFromStackSlot(RVVCSI); `````````` </details> https://github.com/llvm/llvm-project/pull/77560 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits