KanRobert wrote: > > Why not return `i32` for 64-bit mask in 32-bit mode? > > You mean in two `i32` registers? The problem is the inline asm constraint has > 1:1 map with physical register except corner cases. And represent a `k` > constraint into two GPR registers is inefficient.
Is it represented by i64 x 1 in 32-bit mode after this patch? https://github.com/llvm/llvm-project/pull/77733 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
