sfertile created this revision.
sfertile added reviewers: amehsan, kbarton, nemanjai, jtony, syzaara, lei.
sfertile added subscribers: cfe-commits, echristo.
sfertile set the repository for this revision to rL LLVM.
Add macros that implement the vec_extract4b and vec_insert4b functionality.
vector unsigned long long vec_extract4b (vector unsigned char, const int)
Purpose:
Extracts a word from a vector at a byte position.
Result value:
The first doubleword element of the result contains the zero-extended extracted
word from ARG1. The second doubleword is set to 0. ARG2 specifies the
least-significant byte number (0 - 12) of the word to be extracted
vector unsigned char vec_insert4b (vector signed int, vector unsigned char,
const int)
vector unsigned char vec_insert4b (vector unsigned int, vector unsigned char,
const int)
Purpose:
Inserts a word into a vector at a byte position.
Result Value:
The contents of word element 1 of the first argument are extracted and placed
into argument 2 at the byte elements starting at the position indicated by the
third argument.
Repository:
rL LLVM
https://reviews.llvm.org/D26546
Files:
include/clang/Basic/BuiltinsPPC.def
lib/Headers/altivec.h
test/CodeGen/builtins-ppc-p9vector.c
Index: test/CodeGen/builtins-ppc-p9vector.c
===================================================================
--- test/CodeGen/builtins-ppc-p9vector.c
+++ test/CodeGen/builtins-ppc-p9vector.c
@@ -827,4 +827,25 @@
// CHECK-NEXT: ret <16 x i8>
return vec_srv (vuca, vucb);
}
-
+vector unsigned char test74(void) {
+// CHECK-BE: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32>
{{.+}}, <4 x i32> {{.+}}, i32 5)
+// CHECK-BE-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>
+// CHECK: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32>
{{.+}}, <4 x i32> {{.+}}, i32 7)
+// CHECK-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>
+ return vec_insert4b(vuia, vuca, 5);
+}
+vector unsigned char test75(void) {
+// CHECK-BE: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32>
{{.+}}, <4 x i32> {{.+}}, i32 5)
+// CHECK-BE-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>
+// CHECK: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32>
{{.+}}, <4 x i32> {{.+}}, i32 7)
+// CHECK-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>
+ return vec_insert4b(vsia, vuca, 5);
+}
+vector unsigned long long test76(void) {
+// CHECK-BE: [[T1:%.+]] = call <2 x i64> @llvm.ppc.vsx.xxextractuw(<4 x i32>
{{.+}}, i32 11)
+// CHECK-BE-NEXT: ret <2 x i64> [[T1]]
+// CHECK: call <2 x i64> @llvm.ppc.vsx.xxextractuw(<4 x i32> {{.+}}, i32 1)
+// CHECK: [[T1:%.+]] = shufflevector <2 x i64> {{.+}}, <2 x i64> {{.+}}, <2 x
i32> <i32 1, i32 0>
+// CHECK-NEXT: ret <2 x i64> [[T1]]
+ return vec_extract4b(vuca, 11);
+}
Index: lib/Headers/altivec.h
===================================================================
--- lib/Headers/altivec.h
+++ lib/Headers/altivec.h
@@ -11902,6 +11902,16 @@
return __a[__b];
}
+#if defined(__POWER9_VECTOR__)
+#ifdef __LITTLE_ENDIAN__
+#define vec_extract4b(__a, __b)
\
+ vec_reve((vector unsigned long long)
\
+ __builtin_vsx_xxextractuw((__a), (12 - (__b & 0xF))))
+#else
+#define vec_extract4b(__a, __b) __builtin_vsx_xxextractuw((__a), (__b))
+#endif
+#endif /* if defined(__POWER9_VECTOR__) */
+
/* vec_insert */
static __inline__ vector signed char __ATTRS_o_ai
@@ -11993,6 +12003,18 @@
return __b;
}
+#if defined(__POWER9_VECTOR__)
+#ifdef __LITTLE_ENDIAN__
+#define vec_insert4b(__a, __b, __c)
\
+ ((vector unsigned char)__builtin_vsx_xxinsertw((__a),
\
+ vec_reve((vector unsigned long long)(__b)),
\
+ 12 - ((__c) & 0xF)))
+#else
+#define vec_insert4b(__a, __b, __c) \
+ ((vector unsigned char)__builtin_vsx_xxinsertw((__a), (__b), (__c) & 0xF))
+#endif
+#endif /* if defined(__POWER9_VECTOR__) */
+
/* vec_lvlx */
static __inline__ vector signed char __ATTRS_o_ai
Index: include/clang/Basic/BuiltinsPPC.def
===================================================================
--- include/clang/Basic/BuiltinsPPC.def
+++ include/clang/Basic/BuiltinsPPC.def
@@ -380,6 +380,9 @@
BUILTIN(__builtin_vsx_xviexpdp, "V2dV2ULLiV2ULLi", "")
BUILTIN(__builtin_vsx_xviexpsp, "V4fV4UiV4Ui", "")
+BUILTIN(__builtin_vsx_xxinsertw, "V16UcV4UiV16UcIi", "")
+BUILTIN(__builtin_vsx_xxextractuw, "V2ULLiV16UcIi", "")
+
// HTM builtins
BUILTIN(__builtin_tbegin, "UiUIi", "")
BUILTIN(__builtin_tend, "UiUIi", "")
Index: test/CodeGen/builtins-ppc-p9vector.c
===================================================================
--- test/CodeGen/builtins-ppc-p9vector.c
+++ test/CodeGen/builtins-ppc-p9vector.c
@@ -827,4 +827,25 @@
// CHECK-NEXT: ret <16 x i8>
return vec_srv (vuca, vucb);
}
-
+vector unsigned char test74(void) {
+// CHECK-BE: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> {{.+}}, <4 x i32> {{.+}}, i32 5)
+// CHECK-BE-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>
+// CHECK: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> {{.+}}, <4 x i32> {{.+}}, i32 7)
+// CHECK-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>
+ return vec_insert4b(vuia, vuca, 5);
+}
+vector unsigned char test75(void) {
+// CHECK-BE: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> {{.+}}, <4 x i32> {{.+}}, i32 5)
+// CHECK-BE-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>
+// CHECK: [[T1:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> {{.+}}, <4 x i32> {{.+}}, i32 7)
+// CHECK-NEXT: bitcast <4 x i32> [[T1]] to <16 x i8>
+ return vec_insert4b(vsia, vuca, 5);
+}
+vector unsigned long long test76(void) {
+// CHECK-BE: [[T1:%.+]] = call <2 x i64> @llvm.ppc.vsx.xxextractuw(<4 x i32> {{.+}}, i32 11)
+// CHECK-BE-NEXT: ret <2 x i64> [[T1]]
+// CHECK: call <2 x i64> @llvm.ppc.vsx.xxextractuw(<4 x i32> {{.+}}, i32 1)
+// CHECK: [[T1:%.+]] = shufflevector <2 x i64> {{.+}}, <2 x i64> {{.+}}, <2 x i32> <i32 1, i32 0>
+// CHECK-NEXT: ret <2 x i64> [[T1]]
+ return vec_extract4b(vuca, 11);
+}
Index: lib/Headers/altivec.h
===================================================================
--- lib/Headers/altivec.h
+++ lib/Headers/altivec.h
@@ -11902,6 +11902,16 @@
return __a[__b];
}
+#if defined(__POWER9_VECTOR__)
+#ifdef __LITTLE_ENDIAN__
+#define vec_extract4b(__a, __b) \
+ vec_reve((vector unsigned long long) \
+ __builtin_vsx_xxextractuw((__a), (12 - (__b & 0xF))))
+#else
+#define vec_extract4b(__a, __b) __builtin_vsx_xxextractuw((__a), (__b))
+#endif
+#endif /* if defined(__POWER9_VECTOR__) */
+
/* vec_insert */
static __inline__ vector signed char __ATTRS_o_ai
@@ -11993,6 +12003,18 @@
return __b;
}
+#if defined(__POWER9_VECTOR__)
+#ifdef __LITTLE_ENDIAN__
+#define vec_insert4b(__a, __b, __c) \
+ ((vector unsigned char)__builtin_vsx_xxinsertw((__a), \
+ vec_reve((vector unsigned long long)(__b)), \
+ 12 - ((__c) & 0xF)))
+#else
+#define vec_insert4b(__a, __b, __c) \
+ ((vector unsigned char)__builtin_vsx_xxinsertw((__a), (__b), (__c) & 0xF))
+#endif
+#endif /* if defined(__POWER9_VECTOR__) */
+
/* vec_lvlx */
static __inline__ vector signed char __ATTRS_o_ai
Index: include/clang/Basic/BuiltinsPPC.def
===================================================================
--- include/clang/Basic/BuiltinsPPC.def
+++ include/clang/Basic/BuiltinsPPC.def
@@ -380,6 +380,9 @@
BUILTIN(__builtin_vsx_xviexpdp, "V2dV2ULLiV2ULLi", "")
BUILTIN(__builtin_vsx_xviexpsp, "V4fV4UiV4Ui", "")
+BUILTIN(__builtin_vsx_xxinsertw, "V16UcV4UiV16UcIi", "")
+BUILTIN(__builtin_vsx_xxextractuw, "V2ULLiV16UcIi", "")
+
// HTM builtins
BUILTIN(__builtin_tbegin, "UiUIi", "")
BUILTIN(__builtin_tend, "UiUIi", "")
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