Author: YunQiang Su Date: 2024-05-20T14:50:26+08:00 New Revision: 073488cb1f2ca131253efa3171bd56be34ba9fb3
URL: https://github.com/llvm/llvm-project/commit/073488cb1f2ca131253efa3171bd56be34ba9fb3 DIFF: https://github.com/llvm/llvm-project/commit/073488cb1f2ca131253efa3171bd56be34ba9fb3.diff LOG: MIPS/Clang: Use FP32 by default if CPU is mips1 (#92122) FP32 is the only supported FPMode of mips1. FPXX requires MIPS2+ and FP64 requires MIPS32r2+. Added: Modified: clang/lib/Basic/Targets/Mips.h Removed: ################################################################################ diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h index 730deb674aa57..f76c6ece8bf48 100644 --- a/clang/lib/Basic/Targets/Mips.h +++ b/clang/lib/Basic/Targets/Mips.h @@ -85,8 +85,13 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo { return CPU == "mips32r6" || CPU == "mips64r6"; } - bool isFP64Default() const { - return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; + enum FPModeEnum getDefaultFPMode() const { + if (CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64") + return FP64; + else if (CPU == "mips1") + return FP32; + else + return FPXX; } bool isNan2008() const override { return IsNan2008; } @@ -315,8 +320,8 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo { IsSingleFloat = false; FloatABI = HardFloat; DspRev = NoDSP; - FPMode = isFP64Default() ? FP64 : FPXX; NoOddSpreg = false; + FPMode = getDefaultFPMode(); bool OddSpregGiven = false; bool StrictAlign = false; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
