================ @@ -9265,6 +9265,33 @@ multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr,X86VectorVTInfo _, } } +multiclass avx512_fp28_s_ass<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> { + let ExeDomain = _.ExeDomain, hasNoSchedulingInfo = 1 in { + defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst), + (ins _.RC:$src1, _.RC:$src2), OpcodeStr, + "$src2, $src1", "$src1, $src2", + (null_frag)>, Sched<[WriteMove]>; + defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst), + (ins _.RC:$src1, _.RC:$src2), OpcodeStr, + "{sae}, $src2, $src1", "$src1, $src2, {sae}", + (null_frag)>, Sched<[WriteMove]>, EVEX_B; + defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst), + (ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr, + "$src2, $src1", "$src1, $src2", + (null_frag)>, Sched<[WriteMove]>; + } +} + +multiclass avx512_eri_s_ass<bits<8> opc, string OpcodeStr> { + defm SSZ : avx512_fp28_s_ass<opc, OpcodeStr#"ss", f32x_info>, + EVEX_CD8<32, CD8VT1>, VEX_LIG, T8, PD, EVEX, VVVV; + defm SDZ : avx512_fp28_s_ass<opc, OpcodeStr#"sd", f64x_info>, + EVEX_CD8<64, CD8VT1>, VEX_LIG, REX_W, T8, PD, EVEX, VVVV; +} + +defm VRCP28 : avx512_eri_s_ass<0xCB, "vrcp28">; ---------------- phoebewang wrote:
Ok, I recalled we still want the enc/dec support. https://github.com/llvm/llvm-project/pull/92883 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits