================ @@ -58016,15 +58035,27 @@ X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, break; case 'r': // GENERAL_REGS case 'l': // INDEX_REGS + if (Subtarget.useInlineAsmGPR32()) { + if (VT == MVT::i8 || VT == MVT::i1) + return std::make_pair(0U, &X86::GR8_NOREX2RegClass); + if (VT == MVT::i16) + return std::make_pair(0U, &X86::GR16_NOREX2RegClass); + if (VT == MVT::i32 || VT == MVT::f32 || + (!VT.isVector() && !Subtarget.is64Bit())) + return std::make_pair(0U, &X86::GR32_NOREX2RegClass); + if (VT != MVT::f80 && !VT.isVector()) + return std::make_pair(0U, &X86::GR64_NOREX2RegClass); + break; + } if (VT == MVT::i8 || VT == MVT::i1) - return std::make_pair(0U, &X86::GR8_NOREX2RegClass); + return std::make_pair(0U, &X86::GR8RegClass); if (VT == MVT::i16) - return std::make_pair(0U, &X86::GR16_NOREX2RegClass); + return std::make_pair(0U, &X86::GR16RegClass); if (VT == MVT::i32 || VT == MVT::f32 || (!VT.isVector() && !Subtarget.is64Bit())) - return std::make_pair(0U, &X86::GR32_NOREX2RegClass); + return std::make_pair(0U, &X86::GR32RegClass); if (VT != MVT::f80 && !VT.isVector()) - return std::make_pair(0U, &X86::GR64_NOREX2RegClass); + return std::make_pair(0U, &X86::GR64RegClass); ---------------- FreddyLeaf wrote:
you're right. 4a9bf69673a2da02293aa3cf9cab54fbc98a89a2 https://github.com/llvm/llvm-project/pull/92338 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits