[clang] [llvm] [RISCV] Add scheduling model for Syntacore SCR3 (PR #95427)

[Philip Reames via cfe-commits]

================
@@ -326,6 +326,27 @@ def SYNTACORE_SCR1_MAX : 
RISCVProcessorModel<"syntacore-scr1-max",
                                               FeatureStdExtC],
                                              [TuneNoDefaultUnroll]>;
 
+def SYNTACORE_SCR3_RV32 : RISCVProcessorModel<"syntacore-scr3-rv32",
+                                              SyntacoreSCR3RV32Model,
+                                              [Feature32Bit,
+                                               FeatureStdExtI,
+                                               FeatureStdExtZicsr,
+                                               FeatureStdExtZifencei,
+                                               FeatureStdExtM,
+                                               FeatureStdExtC],
+                                              [TuneNoDefaultUnroll, 
FeaturePostRAScheduler]>;
+
+def SYNTACORE_SCR3_RV64 : RISCVProcessorModel<"syntacore-scr3-rv64",
----------------
preames wrote:

This part should really be a standalone change.  Please separate the addition 
of the new processor as it's own PR.

https://github.com/llvm/llvm-project/pull/95427
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