================
@@ -35,6 +35,9 @@ def int_dx_typedBufferLoad_checkbit
def int_dx_typedBufferStore
: DefaultAttrsIntrinsic<[], [llvm_any_ty, llvm_i32_ty, llvm_anyvector_ty]>;
+def int_dx_bufferUpdateCounter
+ : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_any_ty, llvm_i32_ty],
[IntrWriteMem]>;
----------------
tex3d wrote:
No attribute would indicate may read/write memory. However, what about
`IntrInaccessibleMemOrArgMemOnly`? I wonder if that attribute would more
accurately capture what we want. This counter memory is unique and cannot
alias any other memory operations in the module.
https://github.com/llvm/llvm-project/pull/114148
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