https://github.com/labrinea updated https://github.com/llvm/llvm-project/pull/113281
>From 2b416dd0071d45be3f92671f0cb238091689a9dd Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas <alexandros.lamprin...@arm.com> Date: Mon, 21 Oct 2024 17:15:47 +0100 Subject: [PATCH 1/4] [FMV][AArch64] Expand feature dependencies using AArch64::ExtensionSet. Currently we maintain a hand written list of subtarget features which we are implied for a given FMV feature. It is more robust to expand such dependencies using ExtensionDependency from TargetParser, since that is generated by tablegen. For this to work each FMV feature must have a corresponding SubtargetFeature in place. There are a few FMV features which don't satisfy this criteria. We are reviewing them in the ACLE specification. I have also added the missing dependences: * FEAT_DPB2 -> FEAT_DPB * FEAT_FlagM2 -> FEAT_FlagM Blocked on https://github.com/ARM-software/acle/pull/315 --- clang/lib/AST/ASTContext.cpp | 6 +- clang/lib/Basic/Targets/AArch64.cpp | 2 +- clang/test/CodeGen/aarch64-fmv-dependencies.c | 47 ++++--- clang/test/CodeGen/aarch64-targetattr.c | 4 +- clang/test/CodeGen/attr-target-version.c | 58 ++++----- .../Preprocessor/aarch64-target-features.c | 4 +- clang/test/Sema/attr-target-clones-aarch64.c | 2 +- .../llvm/TargetParser/AArch64TargetParser.h | 18 +-- llvm/lib/Target/AArch64/AArch64FMV.td | 116 +++++++++--------- llvm/lib/Target/AArch64/AArch64Features.td | 4 +- llvm/utils/TableGen/ARMTargetDefEmitter.cpp | 17 ++- 11 files changed, 144 insertions(+), 134 deletions(-) diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp index 4bf8ddd762e9a5..fa7c682b9303ef 100644 --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -14251,10 +14251,12 @@ QualType ASTContext::getCorrespondingSignedFixedPointType(QualType Ty) const { static std::vector<std::string> getFMVBackendFeaturesFor( const llvm::SmallVectorImpl<StringRef> &FMVFeatStrings) { std::vector<std::string> BackendFeats; + llvm::AArch64::ExtensionSet FeatureBits; for (StringRef F : FMVFeatStrings) if (auto FMVExt = llvm::AArch64::parseFMVExtension(F)) - for (StringRef F : FMVExt->getImpliedFeatures()) - BackendFeats.push_back(F.str()); + if (FMVExt->ID) + FeatureBits.enable(*FMVExt->ID); + FeatureBits.toLLVMFeatureList(BackendFeats); return BackendFeats; } diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index 3dbba2b4d25bd6..d5b932f76ed9ad 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -722,7 +722,7 @@ unsigned AArch64TargetInfo::multiVersionFeatureCost() const { bool AArch64TargetInfo::doesFeatureAffectCodeGen(StringRef Name) const { // FMV extensions which imply no backend features do not affect codegen. if (auto Ext = llvm::AArch64::parseFMVExtension(Name)) - return !Ext->Features.empty(); + return Ext->ID.has_value(); return false; } diff --git a/clang/test/CodeGen/aarch64-fmv-dependencies.c b/clang/test/CodeGen/aarch64-fmv-dependencies.c index 9aca1b7a9daf6e..bc73d16501e50e 100644 --- a/clang/test/CodeGen/aarch64-fmv-dependencies.c +++ b/clang/test/CodeGen/aarch64-fmv-dependencies.c @@ -3,10 +3,10 @@ // RUN: %clang --target=aarch64-linux-gnu --rtlib=compiler-rt -emit-llvm -S -o - %s | FileCheck %s -// CHECK: define dso_local i32 @fmv._Maes() #[[ATTR0:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Maes() #[[aes:[0-9]+]] { __attribute__((target_version("aes"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Mbf16() #[[bf16_ebf16:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Mbf16() #[[bf16:[0-9]+]] { __attribute__((target_version("bf16"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Mbti() #[[bti:[0-9]+]] { @@ -15,7 +15,7 @@ __attribute__((target_version("bti"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Mcrc() #[[crc:[0-9]+]] { __attribute__((target_version("crc"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Mdgh() #[[ATTR0:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Mdgh() #[[default:[0-9]+]] { __attribute__((target_version("dgh"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Mdit() #[[dit:[0-9]+]] { @@ -30,7 +30,7 @@ __attribute__((target_version("dpb"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Mdpb2() #[[dpb2:[0-9]+]] { __attribute__((target_version("dpb2"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Mebf16() #[[bf16_ebf16:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Mebf16() #[[default]] { __attribute__((target_version("ebf16"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Mf32mm() #[[f32mm:[0-9]+]] { @@ -48,7 +48,7 @@ __attribute__((target_version("flagm"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Mflagm2() #[[flagm2:[0-9]+]] { __attribute__((target_version("flagm2"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Mfp() #[[ATTR0:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Mfp() #[[default]] { __attribute__((target_version("fp"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Mfp16() #[[fp16:[0-9]+]] { @@ -75,13 +75,13 @@ __attribute__((target_version("lse"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Mmemtag() #[[memtag:[0-9]+]] { __attribute__((target_version("memtag"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Mmemtag3() #[[memtag:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Mmemtag3() #[[default]] { __attribute__((target_version("memtag3"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Mmops() #[[mops:[0-9]+]] { __attribute__((target_version("mops"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Mpmull() #[[pmull:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Mpmull() #[[default]] { __attribute__((target_version("pmull"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Mpredres() #[[predres:[0-9]+]] { @@ -90,7 +90,7 @@ __attribute__((target_version("predres"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Mrcpc() #[[rcpc:[0-9]+]] { __attribute__((target_version("rcpc"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Mrcpc2() #[[rcpc:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Mrcpc2() #[[rcpc2:[0-9]+]] { __attribute__((target_version("rcpc2"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Mrcpc3() #[[rcpc3:[0-9]+]] { @@ -102,7 +102,7 @@ __attribute__((target_version("rdm"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Mrng() #[[rng:[0-9]+]] { __attribute__((target_version("rng"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Mrpres() #[[ATTR0:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Mrpres() #[[default]] { __attribute__((target_version("rpres"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Msb() #[[sb:[0-9]+]] { @@ -114,7 +114,7 @@ __attribute__((target_version("sha2"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Msha3() #[[sha3:[0-9]+]] { __attribute__((target_version("sha3"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Msimd() #[[ATTR0:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Msimd() #[[default]] { __attribute__((target_version("simd"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Msm4() #[[sm4:[0-9]+]] { @@ -138,25 +138,25 @@ __attribute__((target_version("ssbs"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Msve() #[[sve:[0-9]+]] { __attribute__((target_version("sve"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Msve-bf16() #[[sve_bf16_ebf16:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Msve-bf16() #[[default]] { __attribute__((target_version("sve-bf16"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Msve-ebf16() #[[sve_bf16_ebf16:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Msve-ebf16() #[[default]] { __attribute__((target_version("sve-ebf16"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Msve-i8mm() #[[sve_i8mm:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Msve-i8mm() #[[default]] { __attribute__((target_version("sve-i8mm"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Msve2() #[[sve2:[0-9]+]] { __attribute__((target_version("sve2"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Msve2-aes() #[[sve2_aes_sve2_pmull128:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Msve2-aes() #[[sve2_aes:[0-9]+]] { __attribute__((target_version("sve2-aes"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Msve2-bitperm() #[[sve2_bitperm:[0-9]+]] { __attribute__((target_version("sve2-bitperm"))) int fmv(void) { return 0; } -// CHECK: define dso_local i32 @fmv._Msve2-pmull128() #[[sve2_aes_sve2_pmull128:[0-9]+]] { +// CHECK: define dso_local i32 @fmv._Msve2-pmull128() #[[default]] { __attribute__((target_version("sve2-pmull128"))) int fmv(void) { return 0; } // CHECK: define dso_local i32 @fmv._Msve2-sha3() #[[sve2_sha3:[0-9]+]] { @@ -177,10 +177,11 @@ int caller() { return fmv(); } -// CHECK: attributes #[[ATTR0]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a" -// CHECK: attributes #[[bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[bf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+v8a" // CHECK: attributes #[[bti]] = { {{.*}} "target-features"="+bti,+fp-armv8,+neon,+outline-atomics,+v8a" // CHECK: attributes #[[crc]] = { {{.*}} "target-features"="+crc,+fp-armv8,+neon,+outline-atomics,+v8a" +// CHECK: attributes #[[default]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a" // CHECK: attributes #[[dit]] = { {{.*}} "target-features"="+dit,+fp-armv8,+neon,+outline-atomics,+v8a" // CHECK: attributes #[[dotprod]] = { {{.*}} "target-features"="+dotprod,+fp-armv8,+neon,+outline-atomics,+v8a" // CHECK: attributes #[[dpb]] = { {{.*}} "target-features"="+ccpp,+fp-armv8,+neon,+outline-atomics,+v8a" @@ -199,10 +200,10 @@ int caller() { // CHECK: attributes #[[lse]] = { {{.*}} "target-features"="+fp-armv8,+lse,+neon,+outline-atomics,+v8a" // CHECK: attributes #[[memtag]] = { {{.*}} "target-features"="+fp-armv8,+mte,+neon,+outline-atomics,+v8a" // CHECK: attributes #[[mops]] = { {{.*}} "target-features"="+fp-armv8,+mops,+neon,+outline-atomics,+v8a" -// CHECK: attributes #[[pmull]] = { {{.*}} "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a" // CHECK: attributes #[[predres]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+predres,+v8a" // CHECK: attributes #[[rcpc]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+v8a" -// CHECK: attributes #[[rcpc3]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+rcpc3,+v8a" +// CHECK: attributes #[[rcpc2]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+rcpc-immo,+v8a" +// CHECK: attributes #[[rcpc3]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rcpc,+rcpc-immo,+rcpc3,+v8a" // CHECK: attributes #[[rdm]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rdm,+v8a" // CHECK: attributes #[[rng]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+rand,+v8a" // CHECK: attributes #[[sb]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+sb,+v8a" @@ -215,11 +216,9 @@ int caller() { // CHECK: attributes #[[sme2]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+neon,+outline-atomics,+sme,+sme2,+v8a" // CHECK: attributes #[[ssbs]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+ssbs,+v8a" // CHECK: attributes #[[sve]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a" -// CHECK: attributes #[[sve_bf16_ebf16]] = { {{.*}} "target-features"="+bf16,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+v8a" -// CHECK: attributes #[[sve_i8mm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+i8mm,+neon,+outline-atomics,+sve,+v8a" // CHECK: attributes #[[sve2]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a" -// CHECK: attributes #[[sve2_aes_sve2_pmull128]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-aes,+v8a" +// CHECK: attributes #[[sve2_aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-aes,+v8a" // CHECK: attributes #[[sve2_bitperm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-bitperm,+v8a" -// CHECK: attributes #[[sve2_sha3]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-sha3,+v8a" -// CHECK: attributes #[[sve2_sm4]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+sve2-sm4,+v8a" +// CHECK: attributes #[[sve2_sha3]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sha2,+sha3,+sve,+sve2,+sve2-sha3,+v8a" +// CHECK: attributes #[[sve2_sm4]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sm4,+sve,+sve2,+sve2-sm4,+v8a" // CHECK: attributes #[[wfxt]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,+wfxt" diff --git a/clang/test/CodeGen/aarch64-targetattr.c b/clang/test/CodeGen/aarch64-targetattr.c index 1bc78a6e1f8c0f..ee7a07244ef9aa 100644 --- a/clang/test/CodeGen/aarch64-targetattr.c +++ b/clang/test/CodeGen/aarch64-targetattr.c @@ -210,8 +210,8 @@ void applem4() {} // CHECK: attributes #[[ATTR7]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "tune-cpu"="generic" } // CHECK: attributes #[[ATTR8]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+crc,+dotprod,+fp-armv8,+fullfp16,+lse,+neon,+perfmon,+ras,+rcpc,+rdm,+sha2,+spe,+ssbs,+v8.1a,+v8.2a,+v8a" "tune-cpu"="cortex-a710" } // CHECK: attributes #[[ATTR9]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" "tune-cpu"="cortex-a710" } -// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" } -// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" } +// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a" } +// CHECK: attributes #[[ATTR11]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-v1" "target-features"="+aes,+bf16,+ccdp,+ccidx,+ccpp,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fp16fml,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+rand,+ras,+rcpc,+rdm,+sha2,+sha3,+sm4,+spe,+ssbs,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8a,-sve" } // CHECK: attributes #[[ATTR12]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" } // CHECK: attributes #[[ATTR13]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16" } // CHECK: attributes #[[ATTR14]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="neoverse-n1" "target-features"="+aes,+bf16,+bti,+ccidx,+complxnum,+crc,+dit,+dotprod,+flagm,+fp-armv8,+fullfp16,+i8mm,+jsconv,+lse,+neon,+pauth,+perfmon,+predres,+ras,+rcpc,+rdm,+sb,+sha2,+spe,+ssbs,+sve,+sve2,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,+v8a" "tune-cpu"="cortex-a710" } diff --git a/clang/test/CodeGen/attr-target-version.c b/clang/test/CodeGen/attr-target-version.c index 0e2c7ad99d81bb..2f44190162d2d2 100644 --- a/clang/test/CodeGen/attr-target-version.c +++ b/clang/test/CodeGen/attr-target-version.c @@ -242,14 +242,14 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp -// CHECK-SAME: () #[[ATTR5]] { +// CHECK-SAME: () #[[ATTR12:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 1 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_two._Msimd -// CHECK-SAME: () #[[ATTR5]] { +// CHECK-SAME: () #[[ATTR13:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 2 // @@ -263,7 +263,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp16Msimd -// CHECK-SAME: () #[[ATTR12:[0-9]+]] { +// CHECK-SAME: () #[[ATTR14:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 4 // @@ -296,7 +296,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_c._Mssbs -// CHECK-SAME: () #[[ATTR13:[0-9]+]] { +// CHECK-SAME: () #[[ATTR15:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret void // @@ -354,14 +354,14 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@unused_with_forward_default_decl._Mmops -// CHECK-SAME: () #[[ATTR15:[0-9]+]] { +// CHECK-SAME: () #[[ATTR17:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_extern_forward_default_decl._Mdotprod -// CHECK-SAME: () #[[ATTR16:[0-9]+]] { +// CHECK-SAME: () #[[ATTR18:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // @@ -375,7 +375,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@unused_with_default_def._Msve -// CHECK-SAME: () #[[ATTR17:[0-9]+]] { +// CHECK-SAME: () #[[ATTR19:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // @@ -389,7 +389,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def._Mfp16 -// CHECK-SAME: () #[[ATTR12]] { +// CHECK-SAME: () #[[ATTR20:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // @@ -410,14 +410,14 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def._Mlse -// CHECK-SAME: () #[[ATTR18:[0-9]+]] { +// CHECK-SAME: () #[[ATTR21:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 1 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@unused_without_default._Mrdm -// CHECK-SAME: () #[[ATTR19:[0-9]+]] { +// CHECK-SAME: () #[[ATTR22:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // @@ -431,14 +431,14 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mjscvt -// CHECK-SAME: () #[[ATTR21:[0-9]+]] { +// CHECK-SAME: () #[[ATTR24:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 1 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mrdm -// CHECK-SAME: () #[[ATTR19]] { +// CHECK-SAME: () #[[ATTR22]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 2 // @@ -618,7 +618,7 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_d._Msb -// CHECK-SAME: () #[[ATTR23:[0-9]+]] { +// CHECK-SAME: () #[[ATTR26:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 0 // @@ -660,112 +660,112 @@ int caller(void) { return used_def_without_default_decl() + used_decl_without_de // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf64mmMpmullMsha2 -// CHECK-SAME: () #[[ATTR24:[0-9]+]] { +// CHECK-SAME: () #[[ATTR27:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 1 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfcmaMfp16MrdmMsme -// CHECK-SAME: () #[[ATTR25:[0-9]+]] { +// CHECK-SAME: () #[[ATTR28:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 2 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf32mmMi8mmMsha3 -// CHECK-SAME: () #[[ATTR26:[0-9]+]] { +// CHECK-SAME: () #[[ATTR29:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 12 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MditMsve-ebf16 -// CHECK-SAME: () #[[ATTR27:[0-9]+]] { +// CHECK-SAME: () #[[ATTR30:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 8 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MdpbMrcpc2 -// CHECK-SAME: () #[[ATTR28:[0-9]+]] { +// CHECK-SAME: () #[[ATTR31:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 6 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mdpb2Mjscvt -// CHECK-SAME: () #[[ATTR29:[0-9]+]] { +// CHECK-SAME: () #[[ATTR32:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 7 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfrinttsMrcpc -// CHECK-SAME: () #[[ATTR30:[0-9]+]] { +// CHECK-SAME: () #[[ATTR33:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 3 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MsveMsve-bf16 -// CHECK-SAME: () #[[ATTR31:[0-9]+]] { +// CHECK-SAME: () #[[ATTR19]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 4 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2-aesMsve2-sha3 -// CHECK-SAME: () #[[ATTR32:[0-9]+]] { +// CHECK-SAME: () #[[ATTR34:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 5 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2Msve2-bitpermMsve2-pmull128 -// CHECK-SAME: () #[[ATTR33:[0-9]+]] { +// CHECK-SAME: () #[[ATTR35:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 9 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMsve2-sm4 -// CHECK-SAME: () #[[ATTR34:[0-9]+]] { +// CHECK-SAME: () #[[ATTR36:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 10 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mmemtag3MmopsMrcpc3 -// CHECK-SAME: () #[[ATTR35:[0-9]+]] { +// CHECK-SAME: () #[[ATTR37:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 11 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMdotprod -// CHECK-SAME: () #[[ATTR16]] { +// CHECK-SAME: () #[[ATTR38:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 13 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16fmlMsimd -// CHECK-SAME: () #[[ATTR36:[0-9]+]] { +// CHECK-SAME: () #[[ATTR39:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 14 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfpMsm4 -// CHECK-SAME: () #[[ATTR37:[0-9]+]] { +// CHECK-SAME: () #[[ATTR40:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 15 // // // CHECK: Function Attrs: noinline nounwind optnone // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MlseMrdm -// CHECK-SAME: () #[[ATTR38:[0-9]+]] { +// CHECK-SAME: () #[[ATTR41:[0-9]+]] { // CHECK-NEXT: entry: // CHECK-NEXT: ret i32 16 // diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c index 418430b0b19b89..283d8bf021092d 100644 --- a/clang/test/Preprocessor/aarch64-target-features.c +++ b/clang/test/Preprocessor/aarch64-target-features.c @@ -335,7 +335,7 @@ // CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2" // CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2" // CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2" -// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8r" "-target-feature" "+ccdp" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+flagm" "-target-feature" "+fp-armv8" "-target-feature" "+fp16fml" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+predres" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb" "-target-feature" "+ssbs" +// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8r" "-target-feature" "+ccdp" "-target-feature" "+ccpp" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+flagm" "-target-feature" "+fp-armv8" "-target-feature" "+fp16fml" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+predres" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb" "-target-feature" "+ssbs" // CHECK-MCPU-M3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2" // CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" // CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+perfmon" "-target-feature" "+sha2" @@ -344,7 +344,7 @@ // CHECK-MCPU-CARMEL: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8.2a" "-target-feature" "+aes" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+sha2" // RUN: %clang -target x86_64-apple-macosx -arch arm64 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64 %s -// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+altnzcv" "-target-feature" "+ccdp" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+fp-armv8" "-target-feature" "+fp16fml" "-target-feature" "+fptoint" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+predres" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+specrestrict" "-target-feature" "+ssbs" +// CHECK-ARCH-ARM64: "-target-cpu" "apple-m1" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.4a" "-target-feature" "+aes" "-target-feature" "+altnzcv" "-target-feature" "+ccdp" "-target-feature" "+ccpp" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+dotprod" "-target-feature" "+flagm" "-target-feature" "+fp-armv8" "-target-feature" "+fp16fml" "-target-feature" "+fptoint" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+predres" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sb" "-target-feature" "+sha2" "-target-feature" "+sha3" "-target-feature" "+specrestrict" "-target-feature" "+ssbs" // RUN: %clang -target x86_64-apple-macosx -arch arm64_32 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64_32 %s // CHECK-ARCH-ARM64_32: "-target-cpu" "apple-s4" "-target-feature" "+zcm" "-target-feature" "+zcz" "-target-feature" "+v8.3a" "-target-feature" "+aes" "-target-feature" "+complxnum" "-target-feature" "+crc" "-target-feature" "+fp-armv8" "-target-feature" "+fullfp16" "-target-feature" "+jsconv" "-target-feature" "+lse" "-target-feature" "+neon" "-target-feature" "+pauth" "-target-feature" "+perfmon" "-target-feature" "+ras" "-target-feature" "+rcpc" "-target-feature" "+rdm" "-target-feature" "+sha2" diff --git a/clang/test/Sema/attr-target-clones-aarch64.c b/clang/test/Sema/attr-target-clones-aarch64.c index 191ca9ba96506d..f2fbd12586e9e7 100644 --- a/clang/test/Sema/attr-target-clones-aarch64.c +++ b/clang/test/Sema/attr-target-clones-aarch64.c @@ -78,4 +78,4 @@ int useage(void) { // expected-error@+1 {{function declaration cannot become a multiversioned function after first usage}} int __attribute__((target_clones("sve2-sha3+ssbs", "sm4"))) mv_after_use(void) { return 1; } // expected-error@+1 {{'main' cannot be a multiversioned function}} -int __attribute__((target_clones("sve-i8mm"))) main() { return 1; } +int __attribute__((target_clones("sve"))) main() { return 1; } diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 12c3aa6024a394..db64919d1feddc 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -68,19 +68,13 @@ struct ExtensionInfo { #include "llvm/TargetParser/AArch64TargetParserDef.inc" struct FMVInfo { - StringRef Name; // The target_version/target_clones spelling. - CPUFeatures Bit; // Index of the bit in the FMV feature bitset. - StringRef Features; // List of SubtargetFeatures to enable. - unsigned Priority; // FMV priority. - FMVInfo(StringRef Name, CPUFeatures Bit, StringRef Features, + StringRef Name; // The target_version/target_clones spelling. + CPUFeatures Bit; // Index of the bit in the FMV feature bitset. + std::optional<ArchExtKind> ID; // The architecture extension to enable. + unsigned Priority; // FMV priority. + FMVInfo(StringRef Name, CPUFeatures Bit, std::optional<ArchExtKind> ID, unsigned Priority) - : Name(Name), Bit(Bit), Features(Features), Priority(Priority){}; - - SmallVector<StringRef, 8> getImpliedFeatures() { - SmallVector<StringRef, 8> Feats; - Features.split(Feats, ',', -1, false); // discard empty strings - return Feats; - } + : Name(Name), Bit(Bit), ID(ID), Priority(Priority){}; }; const std::vector<FMVInfo> &getFMVInfo(); diff --git a/llvm/lib/Target/AArch64/AArch64FMV.td b/llvm/lib/Target/AArch64/AArch64FMV.td index 5674e4dbd56bb7..8e681331d6e371 100644 --- a/llvm/lib/Target/AArch64/AArch64FMV.td +++ b/llvm/lib/Target/AArch64/AArch64FMV.td @@ -22,7 +22,7 @@ // Something you can add to target_version or target_clones. -class FMVExtension<string n, string b, string f, int p> { +class FMVExtension<string n, string b, int p> { // Name, as spelled in target_version or target_clones. e.g. "memtag". string Name = n; @@ -30,65 +30,65 @@ class FMVExtension<string n, string b, string f, int p> { // Currently this is given as a value from the enum "CPUFeatures". string Bit = b; - // SubtargetFeatures enabled for codegen when this FMV feature is present. - string BackendFeatures = f; + // SubtargetFeature enabled for codegen when this FMV feature is present. + string BackendFeature = n; // The FMV priority. int Priority = p; } -def : FMVExtension<"aes", "FEAT_AES", "+fp-armv8,+neon", 150>; -def : FMVExtension<"bf16", "FEAT_BF16", "+bf16", 280>; -def : FMVExtension<"bti", "FEAT_BTI", "+bti", 510>; -def : FMVExtension<"crc", "FEAT_CRC", "+crc", 110>; -def : FMVExtension<"dgh", "FEAT_DGH", "", 260>; -def : FMVExtension<"dit", "FEAT_DIT", "+dit", 180>; -def : FMVExtension<"dotprod", "FEAT_DOTPROD", "+dotprod,+fp-armv8,+neon", 104>; -def : FMVExtension<"dpb", "FEAT_DPB", "+ccpp", 190>; -def : FMVExtension<"dpb2", "FEAT_DPB2", "+ccpp,+ccdp", 200>; -def : FMVExtension<"ebf16", "FEAT_EBF16", "+bf16", 290>; -def : FMVExtension<"f32mm", "FEAT_SVE_F32MM", "+sve,+f32mm,+fullfp16,+fp-armv8,+neon", 350>; -def : FMVExtension<"f64mm", "FEAT_SVE_F64MM", "+sve,+f64mm,+fullfp16,+fp-armv8,+neon", 360>; -def : FMVExtension<"fcma", "FEAT_FCMA", "+fp-armv8,+neon,+complxnum", 220>; -def : FMVExtension<"flagm", "FEAT_FLAGM", "+flagm", 20>; -def : FMVExtension<"flagm2", "FEAT_FLAGM2", "+flagm,+altnzcv", 30>; -def : FMVExtension<"fp", "FEAT_FP", "+fp-armv8,+neon", 90>; -def : FMVExtension<"fp16", "FEAT_FP16", "+fullfp16,+fp-armv8,+neon", 170>; -def : FMVExtension<"fp16fml", "FEAT_FP16FML", "+fp16fml,+fullfp16,+fp-armv8,+neon", 175>; -def : FMVExtension<"frintts", "FEAT_FRINTTS", "+fptoint", 250>; -def : FMVExtension<"i8mm", "FEAT_I8MM", "+i8mm", 270>; -def : FMVExtension<"jscvt", "FEAT_JSCVT", "+fp-armv8,+neon,+jsconv", 210>; -def : FMVExtension<"ls64", "FEAT_LS64_ACCDATA", "+ls64", 520>; -def : FMVExtension<"lse", "FEAT_LSE", "+lse", 80>; -def : FMVExtension<"memtag", "FEAT_MEMTAG2", "+mte", 440>; -def : FMVExtension<"memtag3", "FEAT_MEMTAG3", "+mte", 460>; -def : FMVExtension<"mops", "FEAT_MOPS", "+mops", 650>; -def : FMVExtension<"pmull", "FEAT_PMULL", "+aes,+fp-armv8,+neon", 160>; -def : FMVExtension<"predres", "FEAT_PREDRES", "+predres", 480>; -def : FMVExtension<"rcpc", "FEAT_RCPC", "+rcpc", 230>; -def : FMVExtension<"rcpc2", "FEAT_RCPC2", "+rcpc", 240>; -def : FMVExtension<"rcpc3", "FEAT_RCPC3", "+rcpc,+rcpc3", 241>; -def : FMVExtension<"rdm", "FEAT_RDM", "+rdm,+fp-armv8,+neon", 108>; -def : FMVExtension<"rng", "FEAT_RNG", "+rand", 10>; -def : FMVExtension<"rpres", "FEAT_RPRES", "", 300>; -def : FMVExtension<"sb", "FEAT_SB", "+sb", 470>; -def : FMVExtension<"sha2", "FEAT_SHA2", "+sha2,+fp-armv8,+neon", 130>; -def : FMVExtension<"sha3", "FEAT_SHA3", "+sha3,+sha2,+fp-armv8,+neon", 140>; -def : FMVExtension<"simd", "FEAT_SIMD", "+fp-armv8,+neon", 100>; -def : FMVExtension<"sm4", "FEAT_SM4", "+sm4,+fp-armv8,+neon", 106>; -def : FMVExtension<"sme", "FEAT_SME", "+sme,+bf16", 430>; -def : FMVExtension<"sme-f64f64", "FEAT_SME_F64", "+sme,+sme-f64f64,+bf16", 560>; -def : FMVExtension<"sme-i16i64", "FEAT_SME_I64", "+sme,+sme-i16i64,+bf16", 570>; -def : FMVExtension<"sme2", "FEAT_SME2", "+sme2,+sme,+bf16", 580>; -def : FMVExtension<"ssbs", "FEAT_SSBS2", "+ssbs", 490>; -def : FMVExtension<"sve", "FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>; -def : FMVExtension<"sve-bf16", "FEAT_SVE_BF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 320>; -def : FMVExtension<"sve-ebf16", "FEAT_SVE_EBF16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>; -def : FMVExtension<"sve-i8mm", "FEAT_SVE_I8MM", "+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340>; -def : FMVExtension<"sve2", "FEAT_SVE2", "+sve2,+sve,+fullfp16,+fp-armv8,+neon", 370>; -def : FMVExtension<"sve2-aes", "FEAT_SVE_AES", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 380>; -def : FMVExtension<"sve2-bitperm", "FEAT_SVE_BITPERM", "+sve2,+sve,+sve2-bitperm,+fullfp16,+fp-armv8,+neon", 400>; -def : FMVExtension<"sve2-pmull128", "FEAT_SVE_PMULL128", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390>; -def : FMVExtension<"sve2-sha3", "FEAT_SVE_SHA3", "+sve2,+sve,+sve2-sha3,+fullfp16,+fp-armv8,+neon", 410>; -def : FMVExtension<"sve2-sm4", "FEAT_SVE_SM4", "+sve2,+sve,+sve2-sm4,+fullfp16,+fp-armv8,+neon", 420>; -def : FMVExtension<"wfxt", "FEAT_WFXT", "+wfxt", 550>; +def : FMVExtension<"aes", "FEAT_AES", 150>; +def : FMVExtension<"bf16", "FEAT_BF16", 280>; +def : FMVExtension<"bti", "FEAT_BTI", 510>; +def : FMVExtension<"crc", "FEAT_CRC", 110>; +def : FMVExtension<"dgh", "FEAT_DGH", 260>; +def : FMVExtension<"dit", "FEAT_DIT", 180>; +def : FMVExtension<"dotprod", "FEAT_DOTPROD", 104>; +let BackendFeature = "ccpp" in def : FMVExtension<"dpb", "FEAT_DPB", 190>; +let BackendFeature = "ccdp" in def : FMVExtension<"dpb2", "FEAT_DPB2", 200>; +def : FMVExtension<"ebf16", "FEAT_EBF16", 290>; +def : FMVExtension<"f32mm", "FEAT_SVE_F32MM", 350>; +def : FMVExtension<"f64mm", "FEAT_SVE_F64MM", 360>; +def : FMVExtension<"fcma", "FEAT_FCMA", 220>; +def : FMVExtension<"flagm", "FEAT_FLAGM", 20>; +let BackendFeature = "altnzcv" in def : FMVExtension<"flagm2", "FEAT_FLAGM2", 30>; +def : FMVExtension<"fp", "FEAT_FP", 90>; +def : FMVExtension<"fp16", "FEAT_FP16", 170>; +def : FMVExtension<"fp16fml", "FEAT_FP16FML", 175>; +let BackendFeature = "fptoint" in def : FMVExtension<"frintts", "FEAT_FRINTTS", 250>; +def : FMVExtension<"i8mm", "FEAT_I8MM", 270>; +def : FMVExtension<"jscvt", "FEAT_JSCVT", 210>; +def : FMVExtension<"ls64", "FEAT_LS64_ACCDATA", 520>; +def : FMVExtension<"lse", "FEAT_LSE", 80>; +def : FMVExtension<"memtag", "FEAT_MEMTAG2", 440>; +def : FMVExtension<"memtag3", "FEAT_MEMTAG3", 460>; +def : FMVExtension<"mops", "FEAT_MOPS", 650>; +def : FMVExtension<"pmull", "FEAT_PMULL", 160>; +def : FMVExtension<"predres", "FEAT_PREDRES", 480>; +def : FMVExtension<"rcpc", "FEAT_RCPC", 230>; +let BackendFeature = "rcpc-immo" in def : FMVExtension<"rcpc2", "FEAT_RCPC2", 240>; +def : FMVExtension<"rcpc3", "FEAT_RCPC3", 241>; +def : FMVExtension<"rdm", "FEAT_RDM", 108>; +def : FMVExtension<"rng", "FEAT_RNG", 10>; +def : FMVExtension<"rpres", "FEAT_RPRES", 300>; +def : FMVExtension<"sb", "FEAT_SB", 470>; +def : FMVExtension<"sha2", "FEAT_SHA2", 130>; +def : FMVExtension<"sha3", "FEAT_SHA3", 140>; +def : FMVExtension<"simd", "FEAT_SIMD", 100>; +def : FMVExtension<"sm4", "FEAT_SM4", 106>; +def : FMVExtension<"sme", "FEAT_SME", 430>; +def : FMVExtension<"sme-f64f64", "FEAT_SME_F64", 560>; +def : FMVExtension<"sme-i16i64", "FEAT_SME_I64", 570>; +def : FMVExtension<"sme2", "FEAT_SME2", 580>; +def : FMVExtension<"ssbs", "FEAT_SSBS2", 490>; +def : FMVExtension<"sve", "FEAT_SVE", 310>; +def : FMVExtension<"sve-bf16", "FEAT_SVE_BF16", 320>; +def : FMVExtension<"sve-ebf16", "FEAT_SVE_EBF16", 330>; +def : FMVExtension<"sve-i8mm", "FEAT_SVE_I8MM", 340>; +def : FMVExtension<"sve2", "FEAT_SVE2", 370>; +def : FMVExtension<"sve2-aes", "FEAT_SVE_AES", 380>; +def : FMVExtension<"sve2-bitperm", "FEAT_SVE_BITPERM", 400>; +def : FMVExtension<"sve2-pmull128", "FEAT_SVE_PMULL128", 390>; +def : FMVExtension<"sve2-sha3", "FEAT_SVE_SHA3", 410>; +def : FMVExtension<"sve2-sm4", "FEAT_SVE_SM4", 420>; +def : FMVExtension<"wfxt", "FEAT_WFXT", 550>; diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index 831f311b236441..5d4ac19277078c 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -243,7 +243,7 @@ def FeatureRCPC_IMMO : Extension<"rcpc-immo", "RCPC_IMMO", "FEAT_LRCPC2", //===----------------------------------------------------------------------===// def FeatureAltFPCmp : Extension<"altnzcv", "AlternativeNZCV", "FEAT_FlagM2", - "Enable alternative NZCV format for floating point comparisons">; + "Enable alternative NZCV format for floating point comparisons", [FeatureFlagM]>; def FeatureFRInt3264 : Extension<"fptoint", "FRInt3264", "FEAT_FRINTTS", "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " @@ -259,7 +259,7 @@ def FeaturePredRes : ExtensionWithMArch<"predres", "PredRes", "FEAT_SPECRES", "Enable Armv8.5-A execution and data prediction invalidation instructions">; def FeatureCacheDeepPersist : Extension<"ccdp", "CCDP", "FEAT_DPB2", - "Enable Armv8.5-A Cache Clean to Point of Deep Persistence">; + "Enable Armv8.5-A Cache Clean to Point of Deep Persistence", [FeatureCCPP]>; def FeatureBranchTargetId : ExtensionWithMArch<"bti", "BTI", "FEAT_BTI", "Enable Branch Target Identification">; diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp index 6b8ebf96cdf383..c064f097204f48 100644 --- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp @@ -12,6 +12,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/StringSet.h" #include "llvm/Support/Format.h" #include "llvm/Support/FormatVariadic.h" @@ -78,6 +79,15 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { }; sort(SortedExtensions, Alphabetical); + // Cache Extension records for quick lookup. + DenseMap<StringRef, const Record *> ExtensionMap; + for (const Record *Rec : SortedExtensions) { + auto Name = Rec->getValueAsString("UserVisibleName"); + if (Name.empty()) + Name = Rec->getValueAsString("Name"); + ExtensionMap[Name] = Rec; + } + // The ARMProcFamilyEnum values are initialised by SubtargetFeature defs // which set the ARMProcFamily field. We can generate the enum from these defs // which look like this: @@ -153,7 +163,12 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) { OS << " I.emplace_back("; OS << "\"" << Rec->getValueAsString("Name") << "\""; OS << ", " << Rec->getValueAsString("Bit"); - OS << ", \"" << Rec->getValueAsString("BackendFeatures") << "\""; + auto FeatName = Rec->getValueAsString("BackendFeature"); + const Record *FeatRec = ExtensionMap[FeatName]; + if (FeatRec) + OS << ", " << FeatRec->getValueAsString("ArchExtKindSpelling").upper(); + else + OS << ", std::nullopt"; OS << ", " << (uint64_t)Rec->getValueAsInt("Priority"); OS << ");\n"; }; >From 069f99c60893f552b7297a88cf74a535d32038aa Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas <alexandros.lamprin...@arm.com> Date: Tue, 22 Oct 2024 09:53:35 +0100 Subject: [PATCH 2/4] Update AArch64TargetParser.h clang format --- llvm/include/llvm/TargetParser/AArch64TargetParser.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index db64919d1feddc..d7b1ba511f95d3 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -74,7 +74,7 @@ struct FMVInfo { unsigned Priority; // FMV priority. FMVInfo(StringRef Name, CPUFeatures Bit, std::optional<ArchExtKind> ID, unsigned Priority) - : Name(Name), Bit(Bit), ID(ID), Priority(Priority){}; + : Name(Name), Bit(Bit), ID(ID), Priority(Priority) {}; }; const std::vector<FMVInfo> &getFMVInfo(); >From 695d2f8d3ac84c91a5d3627ee5478c2fa4ba4703 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas <alexandros.lamprin...@arm.com> Date: Fri, 8 Nov 2024 12:14:30 +0000 Subject: [PATCH 3/4] changes from last revision: adds missing dependencies to comply with GCC * i8mm -> simd * bf16 -> fp --- llvm/lib/Target/AArch64/AArch64Features.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index 0faf032b75de43..56ed31dc4f5958 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -160,7 +160,7 @@ def FeatureSVE : ExtensionWithMArch<"sve", "SVE", "FEAT_SVE", let ArchExtKindSpelling = "AEK_I8MM" in def FeatureMatMulInt8 : ExtensionWithMArch<"i8mm", "MatMulInt8", "FEAT_I8MM", - "Enable Matrix Multiply Int8 Extension">; + "Enable Matrix Multiply Int8 Extension", [FeatureNEON]>; let ArchExtKindSpelling = "AEK_F32MM" in def FeatureMatMulFP32 : ExtensionWithMArch<"f32mm", "MatMulFP32", "FEAT_F32MM", @@ -279,7 +279,7 @@ def FeatureMTE : ExtensionWithMArch<"mte", "MTE", "FEAT_MTE, FEAT_MTE2", //===----------------------------------------------------------------------===// def FeatureBF16 : ExtensionWithMArch<"bf16", "BF16", "FEAT_BF16", - "Enable BFloat16 Extension">; + "Enable BFloat16 Extension", [FeatureFPARMv8]>; def FeatureAMVS : Extension<"amvs", "AMVS", "FEAT_AMUv1p1", "Enable Armv8.6-A Activity Monitors Virtualization support", >From 24fc5d78ca255fa3142f3647c591fbded7504a46 Mon Sep 17 00:00:00 2001 From: Alexandros Lamprineas <alexandros.lamprin...@arm.com> Date: Mon, 11 Nov 2024 13:40:55 +0000 Subject: [PATCH 4/4] Reverts 695d2f8d3ac84c91a5d3627ee5478c2fa4ba4703 adds missing dependencies to comply with GCC * i8mm -> simd * bf16 -> fp --- llvm/lib/Target/AArch64/AArch64Features.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index 19661c4819d402..0b4d3e49d66a50 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -160,7 +160,7 @@ def FeatureSVE : ExtensionWithMArch<"sve", "SVE", "FEAT_SVE", let ArchExtKindSpelling = "AEK_I8MM" in def FeatureMatMulInt8 : ExtensionWithMArch<"i8mm", "MatMulInt8", "FEAT_I8MM", - "Enable Matrix Multiply Int8 Extension", [FeatureNEON]>; + "Enable Matrix Multiply Int8 Extension">; let ArchExtKindSpelling = "AEK_F32MM" in def FeatureMatMulFP32 : ExtensionWithMArch<"f32mm", "MatMulFP32", "FEAT_F32MM", @@ -279,7 +279,7 @@ def FeatureMTE : ExtensionWithMArch<"mte", "MTE", "FEAT_MTE, FEAT_MTE2", //===----------------------------------------------------------------------===// def FeatureBF16 : ExtensionWithMArch<"bf16", "BF16", "FEAT_BF16", - "Enable BFloat16 Extension", [FeatureFPARMv8]>; + "Enable BFloat16 Extension">; def FeatureAMVS : Extension<"amvs", "AMVS", "FEAT_AMUv1p1", "Enable Armv8.6-A Activity Monitors Virtualization support", _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits