================
@@ -370,6 +370,71 @@ let Predicates = [HasAMXTRANSPOSE, In64BitMode] in {
}
} // HasAMXTILE, HasAMXTRANSPOSE
+let Predicates = [HasAMXMOVRS, HasAMXTRANSPOSE, In64BitMode], SchedRW =
[WriteSystem] in {
+ def T2RPNTLVWZ0RS : I<0xf8, MRMSrcMemFSIB, (outs TILEPair:$dst),
+ (ins sibmem:$src1),
+ "t2rpntlvwz0rs\t{$src1, $dst|$dst, $src1}",
+ []>, VEX, T_MAP5;
+ def T2RPNTLVWZ0RST1 : I<0xf9, MRMSrcMemFSIB, (outs TILEPair:$dst),
+ (ins sibmem:$src1),
+ "t2rpntlvwz0rst1\t{$src1, $dst|$dst, $src1}",
+ []>, VEX, T_MAP5;
+ def T2RPNTLVWZ1RS : I<0xf8, MRMSrcMemFSIB, (outs TILEPair:$dst),
+ (ins sibmem:$src1),
+ "t2rpntlvwz1rs\t{$src1, $dst|$dst, $src1}",
+ []>, VEX, T_MAP5, PD;
+ def T2RPNTLVWZ1RST1 : I<0xf9, MRMSrcMemFSIB, (outs TILEPair:$dst),
+ (ins sibmem:$src1),
+ "t2rpntlvwz1rst1\t{$src1, $dst|$dst, $src1}",
+ []>, VEX, T_MAP5, PD;
+ let isPseudo = true in {
+ def PT2RPNTLVWZ0RSV : PseudoI<(outs TILEPair:$dst),
+ (ins GR16:$src1, GR16:$src2, GR16:$src3,
opaquemem:$src4),
+ []>;
+ def PT2RPNTLVWZ0RST1V : PseudoI<(outs TILEPair:$dst),
+ (ins GR16:$src1, GR16:$src2, GR16:$src3,
opaquemem:$src4),
+ []>;
+ def PT2RPNTLVWZ1RSV : PseudoI<(outs TILEPair:$dst),
+ (ins GR16:$src1, GR16:$src2, GR16:$src3,
opaquemem:$src4),
+ []>;
+ def PT2RPNTLVWZ1RST1V : PseudoI<(outs TILEPair:$dst),
+ (ins GR16:$src1, GR16:$src2, GR16:$src3,
opaquemem:$src4),
+ []>;
+ }
+ let usesCustomInserter = 1 in {
+ def PT2RPNTLVWZ0RS : PseudoI<(outs), (ins u8imm:$dst, sibmem:$src1), []>;
+ def PT2RPNTLVWZ0RST1 : PseudoI<(outs), (ins u8imm:$dst, sibmem:$src1), []>;
+ def PT2RPNTLVWZ1RS : PseudoI<(outs), (ins u8imm:$dst, sibmem:$src1), []>;
+ def PT2RPNTLVWZ1RST1 : PseudoI<(outs), (ins u8imm:$dst, sibmem:$src1), []>;
+ }
+} // HasAMXMOVRS, HasAMXTRANSPOSE
+
+let Predicates = [HasAMXMOVRS, In64BitMode], SchedRW = [WriteSystem] in {
+ def TILELOADDRS : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst),
+ (ins sibmem:$src1),
+ "tileloaddrs\t{$src1, $dst|$dst, $src1}",
+ []>, VEX, T8, XD;
+ def TILELOADDRST1 : I<0x4a, MRMSrcMemFSIB, (outs TILE:$dst),
+ (ins sibmem:$src1),
+ "tileloaddrst1\t{$src1, $dst|$dst, $src1}",
+ []>, VEX, T8, PD;
+
+ let isPseudo = true, mayLoad = 1 in
----------------
phoebewang wrote:
`let isPseudo = true, mayLoad = 1 in {` to include both.
https://github.com/llvm/llvm-project/pull/115151
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