================
@@ -1883,6 +1931,10 @@ void SystemZInstrInfo::getLoadStoreOpcodes(const
TargetRegisterClass *RC,
} else if (RC == &SystemZ::FP128BitRegClass) {
LoadOpcode = SystemZ::LX;
StoreOpcode = SystemZ::STX;
+ } else if (RC == &SystemZ::FP16BitRegClass ||
+ RC == &SystemZ::VR16BitRegClass) {
+ LoadOpcode = SystemZ::VL16;
----------------
uweigand wrote:
What I meant is that `VL16` is defined as having a `v16hb` return value
```
def VL16 : UnaryAliasVRX<z_load, v16hb, bdxaddr12pair>;
```
and `v16hb` is defined to live in `VR16` - *not* `FP16`:
```
def v16hb : TypedReg<f16, VR16>;
```
So it seems to me forcing a `FP16` register into the instruction, even if it
might seem to do what we want, is not really allowed and might e.g. trigger
strict MI checking failures ...
https://github.com/llvm/llvm-project/pull/109164
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