rengolin added inline comments.
================
Comment at: lib/CodeGen/CGOpenMPRuntime.cpp:6821
+ ISADataTy ISAData[] = {
+ {'n', 64}, // double-word Advanced SIMD
+ {'n', 128}, // quad-word Advanced SIMD
----------------
fpetrogalli wrote:
> rengolin wrote:
> > No f32?
> Sorry, I am not sure to understand what you mean here by f32.
>
> I am considering the double-word registers (64 bits wide) and quad-word
> registers (128 bits wide) that are used in AdvSIMD (NEON) for AArch64 [1].
>
> [1]
> https://developer.arm.com/docs/dui0473/latest/neon-programming/neon-views-of-the-extension-register-bank
Sorry, I meant S0~Sn, but that's silly, as it's VFP. Ignore me.
https://reviews.llvm.org/D30739
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