https://github.com/hchandel updated https://github.com/llvm/llvm-project/pull/124237
>From e83637504f6ddf5b21ca5e7351c7b83236f360b5 Mon Sep 17 00:00:00 2001 From: Harsh Chandel <hchan...@qti.qualcomm.com> Date: Fri, 24 Jan 2025 12:38:13 +0530 Subject: [PATCH 1/2] [RISCV] Renaming muladdi to muliadd as per v0.5 spec. NFC muliadd is more relevant to the operation performed, i.e. multiply by immediate. The latest spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest Change-Id: I0cb141c72da003f56ce54fe3235684a7e92b403f --- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 8 +++---- llvm/test/MC/RISCV/xqciac-invalid.s | 16 +++++++------- llvm/test/MC/RISCV/xqciac-valid.s | 24 ++++++++++----------- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index f746cce8c9a0f1..1f042b0f47e968 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -299,9 +299,9 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { let Predicates = [HasVendorXqciac, IsRV32], DecoderNamespace = "Xqciac" in { let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { - def QC_C_MULADDI : RVInst16CL<0b001, 0b10, (outs GPRC:$rd_wb), + def QC_C_MULIADD : RVInst16CL<0b001, 0b10, (outs GPRC:$rd_wb), (ins GPRC:$rd, GPRC:$rs1, uimm5:$uimm), - "qc.c.muladdi", "$rd, $rs1, $uimm"> { + "qc.c.muliadd", "$rd, $rs1, $uimm"> { let Constraints = "$rd = $rd_wb"; bits<5> uimm; @@ -310,9 +310,9 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { let Inst{5} = uimm{4}; } - def QC_MULADDI : RVInstI<0b110, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb), + def QC_MULIADD : RVInstI<0b110, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, GPRNoX0:$rs1, simm12:$imm12), - "qc.muladdi", "$rd, $rs1, $imm12"> { + "qc.muliadd", "$rd, $rs1, $imm12"> { let Constraints = "$rd = $rd_wb"; } diff --git a/llvm/test/MC/RISCV/xqciac-invalid.s b/llvm/test/MC/RISCV/xqciac-invalid.s index 4e0182aff9cc2c..c595888ddee3e8 100644 --- a/llvm/test/MC/RISCV/xqciac-invalid.s +++ b/llvm/test/MC/RISCV/xqciac-invalid.s @@ -5,29 +5,29 @@ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-EXT %s # CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction -qc.c.muladdi x5, x10, 4 +qc.c.muliadd x5, x10, 4 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction -qc.c.muladdi x15 +qc.c.muliadd x15 # CHECK-IMM: :[[@LINE+1]]:24: error: immediate must be an integer in the range [0, 31] -qc.c.muladdi x10, x15, 32 +qc.c.muliadd x10, x15, 32 # CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension) -qc.c.muladdi x10, x15, 20 +qc.c.muliadd x10, x15, 20 # CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction -qc.muladdi x0, x10, 1048577 +qc.muliadd x0, x10, 1048577 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction -qc.muladdi x10 +qc.muliadd x10 # CHECK-IMM: :[[@LINE+1]]:22: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047] -qc.muladdi x10, x15, 8589934592 +qc.muliadd x10, x15, 8589934592 # CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension) -qc.muladdi x10, x15, 577 +qc.muliadd x10, x15, 577 # CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/xqciac-valid.s b/llvm/test/MC/RISCV/xqciac-valid.s index 6e97d8cc447e14..c786d7c4ea51db 100644 --- a/llvm/test/MC/RISCV/xqciac-valid.s +++ b/llvm/test/MC/RISCV/xqciac-valid.s @@ -10,30 +10,30 @@ # RUN: | llvm-objdump --mattr=+experimental-xqciac --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# CHECK-INST: qc.c.muladdi a0, a1, 0 +# CHECK-INST: qc.c.muliadd a0, a1, 0 # CHECK-ENC: encoding: [0x8a,0x21] -qc.c.muladdi x10, x11, 0 +qc.c.muliadd x10, x11, 0 -# CHECK-INST: qc.c.muladdi a0, a1, 31 +# CHECK-INST: qc.c.muliadd a0, a1, 31 # CHECK-ENC: encoding: [0xea,0x3d] -qc.c.muladdi x10, x11, 31 +qc.c.muliadd x10, x11, 31 -# CHECK-INST: qc.c.muladdi a0, a1, 16 +# CHECK-INST: qc.c.muliadd a0, a1, 16 # CHECK-ENC: encoding: [0xaa,0x21] -qc.c.muladdi x10, x11, 16 +qc.c.muliadd x10, x11, 16 -# CHECK-INST: qc.muladdi tp, t0, 1234 +# CHECK-INST: qc.muliadd tp, t0, 1234 # CHECK-ENC: encoding: [0x0b,0xe2,0x22,0x4d] -qc.muladdi x4, x5, 1234 +qc.muliadd x4, x5, 1234 -# CHECK-INST: qc.muladdi a0, a1, -2048 +# CHECK-INST: qc.muliadd a0, a1, -2048 # CHECK-ENC: encoding: [0x0b,0xe5,0x05,0x80] -qc.muladdi x10, x11, -2048 +qc.muliadd x10, x11, -2048 -# CHECK-INST: qc.muladdi a0, a1, 2047 +# CHECK-INST: qc.muliadd a0, a1, 2047 # CHECK-ENC: encoding: [0x0b,0xe5,0xf5,0x7f] -qc.muladdi x10, x11, 2047 +qc.muliadd x10, x11, 2047 # CHECK-INST: qc.shladd tp, t0, t1, 12 >From 9674607bb9437d3a9fe09174d462722f1e370b2e Mon Sep 17 00:00:00 2001 From: Harsh Chandel <hchan...@qti.qualcomm.com> Date: Mon, 27 Jan 2025 15:52:47 +0530 Subject: [PATCH 2/2] Update extension version for Xqciac as per v0.5 spec Change-Id: I25ab95b88cbf571c2a82f6236d23b0a1dc26e068 --- clang/test/Driver/print-supported-extensions-riscv.c | 2 +- llvm/docs/RISCVUsage.rst | 2 +- llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +- llvm/test/CodeGen/RISCV/attributes.ll | 2 +- llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 4 ++-- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index ae3a1c29df3976..c72b65316ae8a9 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -191,7 +191,7 @@ // CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level) // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) // CHECK-NEXT: xqcia 0.2 'Xqcia' (Qualcomm uC Arithmetic Extension) -// CHECK-NEXT: xqciac 0.2 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension) +// CHECK-NEXT: xqciac 0.3 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension) // CHECK-NEXT: xqcicli 0.2 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) // CHECK-NEXT: xqcicm 0.2 'Xqcicm' (Qualcomm uC Conditional Move Extension) // CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index c83fd1db0ba9b5..71927d57a8f0f9 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -433,7 +433,7 @@ The current vendor extensions supported are: LLVM implements `version 0.2 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. ``experimental-Xqciac`` - LLVM implements `version 0.2 of the Qualcomm uC Load-Store Address Calculation extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. + LLVM implements `version 0.3 of the Qualcomm uC Load-Store Address Calculation extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. ``experimental-Xqcicli`` LLVM implements `version 0.2 of the Qualcomm uC Conditional Load Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32. diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 4119dd77804f1a..a8f433ea91387d 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1279,7 +1279,7 @@ def HasVendorXqcilsm "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)">; def FeatureVendorXqciac - : RISCVExperimentalExtension<0, 2, "Qualcomm uC Load-Store Address Calculation Extension", + : RISCVExperimentalExtension<0, 3, "Qualcomm uC Load-Store Address Calculation Extension", [FeatureStdExtZca]>; def HasVendorXqciac : Predicate<"Subtarget->hasVendorXqciac()">, diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index caed0bdfb04984..b9d5bf0a7227cd 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -398,7 +398,7 @@ ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0" ; RV32XWCHC: .attribute 5, "rv32i2p1_xwchc2p2" ; RV32XQCIA: .attribute 5, "rv32i2p1_xqcia0p2" -; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p2" +; RV32XQCIAC: .attribute 5, "rv32i2p1_zca1p0_xqciac0p3" ; RV32XQCICLI: .attribute 5, "rv32i2p1_xqcicli0p2" ; RV32XQCICM: .attribute 5, "rv32i2p1_zca1p0_xqcicm0p2" ; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 14a60c1857f24f..aa8851e4897e26 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -654,7 +654,7 @@ TEST(ParseArchString, RejectsConflictingExtensions) { } for (StringRef Input : - {"rv64i_xqcisls0p2", "rv64i_xqcia0p2", "rv64i_xqciac0p2", + {"rv64i_xqcisls0p2", "rv64i_xqcia0p2", "rv64i_xqciac0p3", "rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcicm0p2", "rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p2", "rv64i_xqcilo0p2"}) { @@ -1117,7 +1117,7 @@ Experimental extensions ssctr 1.0 svukte 0.3 xqcia 0.2 - xqciac 0.2 + xqciac 0.3 xqcicli 0.2 xqcicm 0.2 xqcics 0.2 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
