llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clangir Author: None (Andres-Salamanca) <details> <summary>Changes</summary> This introduces support for the following cir::case kinds: - `Equal` - `AnyOf` - `Range` --- Full diff: https://github.com/llvm/llvm-project/pull/138003.diff 4 Files Affected: - (modified) clang/include/clang/CIR/MissingFeatures.h (-1) - (modified) clang/lib/CIR/CodeGen/CIRGenFunction.h (+8) - (modified) clang/lib/CIR/CodeGen/CIRGenStmt.cpp (+65-16) - (modified) clang/test/CIR/CodeGen/switch.cpp (+236-11) ``````````diff diff --git a/clang/include/clang/CIR/MissingFeatures.h b/clang/include/clang/CIR/MissingFeatures.h index 4d4951aa0e126..8f58e10d9070e 100644 --- a/clang/include/clang/CIR/MissingFeatures.h +++ b/clang/include/clang/CIR/MissingFeatures.h @@ -161,7 +161,6 @@ struct MissingFeatures { static bool targetSpecificCXXABI() { return false; } static bool moduleNameHash() { return false; } static bool setDSOLocal() { return false; } - static bool foldCaseStmt() { return false; } static bool constantFoldSwitchStatement() { return false; } // Missing types diff --git a/clang/lib/CIR/CodeGen/CIRGenFunction.h b/clang/lib/CIR/CodeGen/CIRGenFunction.h index 592d39930089d..fb1a7dc75161d 100644 --- a/clang/lib/CIR/CodeGen/CIRGenFunction.h +++ b/clang/lib/CIR/CodeGen/CIRGenFunction.h @@ -278,6 +278,9 @@ class CIRGenFunction : public CIRGenTypeCache { /// addressed later. RValue getUndefRValue(clang::QualType ty); + const CaseStmt *foldCaseStmt(const clang::CaseStmt &s, mlir::Type condType, + mlir::ArrayAttr &value, cir::CaseOpKind &kind); + cir::FuncOp generateCode(clang::GlobalDecl gd, cir::FuncOp fn, cir::FuncType funcType); @@ -532,6 +535,11 @@ class CIRGenFunction : public CIRGenTypeCache { mlir::LogicalResult emitDeclStmt(const clang::DeclStmt &s); LValue emitDeclRefLValue(const clang::DeclRefExpr *e); + + mlir::LogicalResult emitDefaultStmt(const clang::DefaultStmt &s, + mlir::Type condType, + bool buildingTopLevelCase); + /// Emit an `if` on a boolean condition to the specified blocks. /// FIXME: Based on the condition, this might try to simplify the codegen of /// the conditional based on the branch. diff --git a/clang/lib/CIR/CodeGen/CIRGenStmt.cpp b/clang/lib/CIR/CodeGen/CIRGenStmt.cpp index 31e29e7828156..56e9ba04c8ce0 100644 --- a/clang/lib/CIR/CodeGen/CIRGenStmt.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenStmt.cpp @@ -253,6 +253,7 @@ mlir::LogicalResult CIRGenFunction::emitSimpleStmt(const Stmt *s, case Stmt::NullStmtClass: break; case Stmt::CaseStmtClass: + case Stmt::DefaultStmtClass: // If we reached here, we must not handling a switch case in the top level. return emitSwitchCase(cast<SwitchCase>(*s), /*buildingTopLevelCase=*/false); @@ -428,6 +429,53 @@ mlir::LogicalResult CIRGenFunction::emitBreakStmt(const clang::BreakStmt &s) { return mlir::success(); } + +const CaseStmt *CIRGenFunction::foldCaseStmt(const clang::CaseStmt &s, + mlir::Type condType, + mlir::ArrayAttr &value, + cir::CaseOpKind &kind) { + const CaseStmt *caseStmt = &s; + const CaseStmt *lastCase = &s; + SmallVector<mlir::Attribute, 4> caseEltValueListAttr; + + // Fold cascading cases whenever possible to simplify codegen a bit. + while (caseStmt) { + lastCase = caseStmt; + + auto intVal = caseStmt->getLHS()->EvaluateKnownConstInt(getContext()); + + if (auto *rhs = caseStmt->getRHS()) { + auto endVal = rhs->EvaluateKnownConstInt(getContext()); + SmallVector<mlir::Attribute, 4> rangeCaseAttr = { + cir::IntAttr::get(condType, intVal), + cir::IntAttr::get(condType, endVal)}; + value = builder.getArrayAttr(rangeCaseAttr); + kind = cir::CaseOpKind::Range; + + // We may not be able to fold rangaes. Due to we can't present range case + // with other trivial cases now. + return caseStmt; + } + + caseEltValueListAttr.push_back(cir::IntAttr::get(condType, intVal)); + + caseStmt = dyn_cast_or_null<CaseStmt>(caseStmt->getSubStmt()); + + // Break early if we found ranges. We can't fold ranges due to the same + // reason above. + if (caseStmt && caseStmt->getRHS()) + break; + } + + if (!caseEltValueListAttr.empty()) { + value = builder.getArrayAttr(caseEltValueListAttr); + kind = caseEltValueListAttr.size() > 1 ? cir::CaseOpKind::Anyof + : cir::CaseOpKind::Equal; + } + + return lastCase; +} + template <typename T> mlir::LogicalResult CIRGenFunction::emitCaseDefaultCascade(const T *stmt, mlir::Type condType, @@ -500,8 +548,8 @@ CIRGenFunction::emitCaseDefaultCascade(const T *stmt, mlir::Type condType, if (subStmtKind == SubStmtKind::Case) { result = emitCaseStmt(*cast<CaseStmt>(sub), condType, buildingTopLevelCase); } else if (subStmtKind == SubStmtKind::Default) { - getCIRGenModule().errorNYI(sub->getSourceRange(), "Default case"); - return mlir::failure(); + result = emitDefaultStmt(*cast<DefaultStmt>(sub), condType, + buildingTopLevelCase); } else if (buildingTopLevelCase) { // If we're building a top level case, try to restore the insert point to // the case we're building, then we can attach more random stmts to the @@ -515,19 +563,21 @@ CIRGenFunction::emitCaseDefaultCascade(const T *stmt, mlir::Type condType, mlir::LogicalResult CIRGenFunction::emitCaseStmt(const CaseStmt &s, mlir::Type condType, bool buildingTopLevelCase) { - llvm::APSInt intVal = s.getLHS()->EvaluateKnownConstInt(getContext()); - SmallVector<mlir::Attribute, 1> caseEltValueListAttr; - caseEltValueListAttr.push_back(cir::IntAttr::get(condType, intVal)); - mlir::ArrayAttr value = builder.getArrayAttr(caseEltValueListAttr); - if (s.getRHS()) { - getCIRGenModule().errorNYI(s.getSourceRange(), "SwitchOp range kind"); - return mlir::failure(); - } - assert(!cir::MissingFeatures::foldCaseStmt()); - return emitCaseDefaultCascade(&s, condType, value, cir::CaseOpKind::Equal, + cir::CaseOpKind kind; + mlir::ArrayAttr value; + const CaseStmt *caseStmt = foldCaseStmt(s, condType, value, kind); + return emitCaseDefaultCascade(caseStmt, condType, value, kind, buildingTopLevelCase); } + + mlir::LogicalResult CIRGenFunction::emitDefaultStmt(const clang::DefaultStmt &s, + mlir::Type condType, + bool buildingTopLevelCase) { + return emitCaseDefaultCascade(&s, condType, builder.getArrayAttr({}), + cir::CaseOpKind::Default, buildingTopLevelCase); +} + mlir::LogicalResult CIRGenFunction::emitSwitchCase(const SwitchCase &s, bool buildingTopLevelCase) { assert(!condTypeStack.empty() && @@ -537,10 +587,9 @@ mlir::LogicalResult CIRGenFunction::emitSwitchCase(const SwitchCase &s, return emitCaseStmt(cast<CaseStmt>(s), condTypeStack.back(), buildingTopLevelCase); - if (s.getStmtClass() == Stmt::DefaultStmtClass) { - getCIRGenModule().errorNYI(s.getSourceRange(), "Default case"); - return mlir::failure(); - } + if (s.getStmtClass() == Stmt::DefaultStmtClass) + return emitDefaultStmt(cast<DefaultStmt>(s), condTypeStack.back(), + buildingTopLevelCase); llvm_unreachable("expect case or default stmt"); } diff --git a/clang/test/CIR/CodeGen/switch.cpp b/clang/test/CIR/CodeGen/switch.cpp index 36523755376a1..ea0e95e7eb553 100644 --- a/clang/test/CIR/CodeGen/switch.cpp +++ b/clang/test/CIR/CodeGen/switch.cpp @@ -16,6 +16,7 @@ void sw1(int a) { } } } + // CIR: cir.func @_Z3sw1i // CIR: cir.switch (%3 : !s32i) { // CIR-NEXT: cir.case(equal, [#cir.int<0> : !s32i]) { @@ -91,12 +92,40 @@ void sw2(int a) { // OGCG: [[SW_EPILOG]]: // OGCG: ret void +void sw3(int a) { + switch (a) { + default: + break; + } +} + +// CIR: cir.func @_Z3sw3i +// CIR: cir.scope { +// CIR-NEXT: %1 = cir.load %0 : !cir.ptr<!s32i>, !s32i +// CIR-NEXT: cir.switch (%1 : !s32i) { +// CIR-NEXT: cir.case(default, []) { +// CIR-NEXT: cir.break +// CIR-NEXT: } +// CIR-NEXT: cir.yield +// CIR-NEXT: } + +// OGCG: define dso_local void @_Z3sw3i +// OGCG: entry: +// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4 +// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4 +// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [ +// OGCG: [[DEFAULT]]: +// OGCG: br label %[[EPILOG:.*]] +// OGCG: [[EPILOG]]: +// OGCG: ret void + int sw4(int a) { switch (a) { case 42: { return 3; } - // TODO: add default case when it is upstreamed + default: + return 2; } return 0; } @@ -112,24 +141,31 @@ int sw4(int a) { // CIR-NEXT: } // CIR-NEXT: cir.yield // CIR-NEXT: } +// CIR-NEXT: cir.case(default, []) { +// CIR-NEXT: %5 = cir.const #cir.int<2> : !s32i +// CIR-NEXT: cir.store %5, %1 : !s32i, !cir.ptr<!s32i> +// CIR-NEXT: %6 = cir.load %1 : !cir.ptr<!s32i>, !s32i +// CIR-NEXT: cir.return %6 : !s32i +// CIR-NEXT: } +// CIR-NEXT: cir.yield +// CIR-NEXT: } // OGCG: define dso_local noundef i32 @_Z3sw4i // OGCG: entry: // OGCG: %[[RETVAL:.*]] = alloca i32, align 4 // OGCG: %[[A_ADDR:.*]] = alloca i32, align 4 // OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4 -// OGCG: switch i32 %[[A_VAL]], label %[[EPILOG:.*]] [ +// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [ // OGCG: i32 42, label %[[SW42:.*]] // OGCG: ] // OGCG: [[SW42]]: // OGCG: br label %[[RETURN:.*]] -// OGCG: [[EPILOG]]: +// OGCG: [[DEFAULT]]: // OGCG: br label %[[RETURN]] // OGCG: [[RETURN]]: // OGCG: %[[RETVAL_LOAD:.*]] = load i32, ptr %[[RETVAL]], align 4 // OGCG: ret i32 %[[RETVAL_LOAD]] - void sw5(int a) { switch (a) { case 1:; @@ -156,13 +192,97 @@ void sw5(int a) { // OGCG: [[SW_EPILOG]]: // OGCG: ret void +void sw6(int a) { + switch (a) { + case 0: + case 1: + case 2: + break; + case 3: + case 4: + case 5: + break; + } +} + +// CIR: cir.func @_Z3sw6i +// CIR: cir.switch (%1 : !s32i) { +// CIR-NEXT: cir.case(anyof, [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i]) { +// CIR-NEXT: cir.break +// CIR-NEXT: } +// CIR-NEXT: cir.case(anyof, [#cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i]) { +// CIR-NEXT: cir.break +// CIR-NEXT: } + +// OGCG: define dso_local void @_Z3sw6i +// OGCG: entry: +// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4 +// OGCG: store i32 %a, ptr %[[A_ADDR]], align 4 +// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4 +// OGCG: switch i32 %[[A_VAL]], label %[[EPILOG:.*]] [ +// OGCG: i32 0, label %[[BB0:.*]] +// OGCG: i32 1, label %[[BB0]] +// OGCG: i32 2, label %[[BB0]] +// OGCG: i32 3, label %[[BB1:.*]] +// OGCG: i32 4, label %[[BB1]] +// OGCG: i32 5, label %[[BB1]] +// OGCG: ] +// OGCG: [[BB0]]: +// OGCG: br label %[[EPILOG]] +// OGCG: [[BB1]]: +// OGCG: br label %[[EPILOG]] +// OGCG: [[EPILOG]]: +// OGCG: ret void + +void sw7(int a) { + switch (a) { + case 0: + case 1: + case 2: + int x; + case 3: + case 4: + case 5: + break; + } +} + +// CIR: cir.func @_Z3sw7i +// CIR: cir.case(anyof, [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i]) { +// CIR-NEXT: cir.yield +// CIR-NEXT: } +// CIR-NEXT: cir.case(anyof, [#cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i]) { +// CIR-NEXT: cir.break +// CIR-NEXT: } + + +// OGCG: define dso_local void @_Z3sw7i +// OGCG: entry: +// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4 +// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4 +// OGCG: switch i32 %[[A_VAL]], label %[[EPILOG:.*]] [ +// OGCG: i32 0, label %[[BB0:.*]] +// OGCG: i32 1, label %[[BB0]] +// OGCG: i32 2, label %[[BB0]] +// OGCG: i32 3, label %[[BB1:.*]] +// OGCG: i32 4, label %[[BB1]] +// OGCG: i32 5, label %[[BB1]] +// OGCG: ] +// OGCG: [[BB0]]: +// OGCG: br label %[[BB1]] +// OGCG: [[BB1]]: +// OGCG: br label %[[EPILOG]] +// OGCG: [[EPILOG]]: +// OGCG: ret void + + void sw8(int a) { switch (a) { case 3: break; case 4: - // TODO: add default case when it is upstreamed + default: break; } } @@ -172,6 +292,9 @@ void sw8(int a) { // CIR-NEXT: cir.break // CIR-NEXT: } // CIR-NEXT: cir.case(equal, [#cir.int<4> : !s32i]) { +// CIR-NEXT: cir.yield +// CIR-NEXT: } +// CIR-NEXT: cir.case(default, []) { // CIR-NEXT: cir.break // CIR-NEXT: } @@ -180,24 +303,25 @@ void sw8(int a) { // OGCG: entry: // OGCG: %[[A_ADDR:.*]] = alloca i32, align 4 // OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4 -// OGCG: switch i32 %[[A_VAL]], label %[[EPILOG:.*]] [ +// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [ // OGCG: i32 3, label %[[SW3:.*]] // OGCG: i32 4, label %[[SW4:.*]] // OGCG: ] // OGCG: [[SW3]]: -// OGCG: br label %[[EPILOG]] +// OGCG: br label %[[EPILOG:.*]] // OGCG: [[SW4]]: +// OGCG: br label %[[DEFAULT]] +// OGCG: [[DEFAULT]]: // OGCG: br label %[[EPILOG]] // OGCG: [[EPILOG]]: // OGCG: ret void - void sw9(int a) { switch (a) { case 3: break; - // TODO: add default case when it is upstreamed + default: case 4: break; } @@ -207,6 +331,9 @@ void sw9(int a) { // CIR: cir.case(equal, [#cir.int<3> : !s32i]) { // CIR-NEXT: cir.break // CIR-NEXT: } +// CIR-NEXT: cir.case(default, []) { +// CIR-NEXT: cir.yield +// CIR-NEXT: } // CIR-NEXT: cir.case(equal, [#cir.int<4> : !s32i]) { // CIR-NEXT: cir.break // CIR-NEXT: } @@ -215,17 +342,115 @@ void sw9(int a) { // OGCG: entry: // OGCG: %[[A_ADDR:.*]] = alloca i32, align 4 // OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4 -// OGCG: switch i32 %[[A_VAL]], label %[[EPILOG:.*]] [ +// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [ // OGCG: i32 3, label %[[SW3:.*]] // OGCG: i32 4, label %[[SW4:.*]] // OGCG: ] // OGCG: [[SW3]]: -// OGCG: br label %[[EPILOG]] +// OGCG: br label %[[EPILOG:.*]] +// OGCG: [[DEFAULT]]: +// OGCG: br label %[[SW4]] // OGCG: [[SW4]]: // OGCG: br label %[[EPILOG]] // OGCG: [[EPILOG]]: // OGCG: ret void +void sw10(int a) { + switch (a) + { + case 3: + break; + case 4: + default: + case 5: + break; + } +} + +//CIR: cir.func @_Z4sw10i +//CIR: cir.case(equal, [#cir.int<3> : !s32i]) { +//CIR-NEXT: cir.break +//CIR-NEXT: } +//CIR-NEXT: cir.case(equal, [#cir.int<4> : !s32i]) { +//CIR-NEXT: cir.yield +//CIR-NEXT: } +//CIR-NEXT: cir.case(default, []) { +//CIR-NEXT: cir.yield +//CIR-NEXT: } +//CIR-NEXT: cir.case(equal, [#cir.int<5> : !s32i]) { +//CIR-NEXT: cir.break +//CIR-NEXT: } + +// OGCG: define dso_local void @_Z4sw10i +// OGCG: entry: +// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4 +// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4 +// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [ +// OGCG: i32 3, label %[[BB3:.*]] +// OGCG: i32 4, label %[[BB4:.*]] +// OGCG: i32 5, label %[[BB5:.*]] +// OGCG: ] +// OGCG: [[BB3]]: +// OGCG: br label %[[EPILOG:.*]] +// OGCG: [[BB4]]: +// OGCG: br label %[[DEFAULT]] +// OGCG: [[DEFAULT]]: +// OGCG: br label %[[BB5]] +// OGCG: [[BB5]]: +// OGCG: br label %[[EPILOG]] +// OGCG: [[EPILOG]]: +// OGCG: ret void + +void sw11(int a) { + switch (a) + { + case 3: + break; + case 4: + case 5: + default: + case 6: + case 7: + break; + } +} + +//CIR: cir.func @_Z4sw11i +//CIR: cir.case(equal, [#cir.int<3> : !s32i]) { +//CIR-NEXT: cir.break +//CIR-NEXT: } +//CIR-NEXT: cir.case(anyof, [#cir.int<4> : !s32i, #cir.int<5> : !s32i]) { +//CIR-NEXT: cir.yield +//CIR-NEXT: } +//CIR-NEXT: cir.case(default, []) { +//CIR-NEXT: cir.yield +//CIR-NEXT: } +//CIR-NEXT: cir.case(anyof, [#cir.int<6> : !s32i, #cir.int<7> : !s32i]) { +//CIR-NEXT: cir.break +//CIR-NEXT: } + +// OGCG: define dso_local void @_Z4sw11i +// OGCG: entry: +// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4 +// OGCG: %[[A_VAL:.*]] = load i32, ptr %[[A_ADDR]], align 4 +// OGCG: switch i32 %[[A_VAL]], label %[[DEFAULT:.*]] [ +// OGCG: i32 3, label %[[BB3:.*]] +// OGCG: i32 4, label %[[BB4:.*]] +// OGCG: i32 5, label %[[BB4]] +// OGCG: i32 6, label %[[BB6:.*]] +// OGCG: i32 7, label %[[BB6]] +// OGCG: ] +// OGCG: [[BB3]]: +// OGCG: br label %[[EPILOG:.*]] +// OGCG: [[BB4]]: +// OGCG: br label %[[DEFAULT]] +// OGCG: [[DEFAULT]]: +// OGCG: br label %[[BB6]] +// OGCG: [[BB6]]: +// OGCG: br label %[[EPILOG]] +// OGCG: [[EPILOG]]: +// OGCG: ret void + void sw12(int a) { switch (a) { `````````` </details> https://github.com/llvm/llvm-project/pull/138003 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
