================ @@ -766,6 +776,9 @@ void RISCVInstrInfo::loadRegFromStackSlot( } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { Opcode = RISCV::FLD; IsScalableVector = false; + } else if (RISCV::FPR128RegClass.hasSubClassEq(RC)) { ---------------- topperc wrote:
This isn't an MC layer change and can't be tested. https://github.com/llvm/llvm-project/pull/139369 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits