================
@@ -571,6 +571,41 @@ void VectorTest(uint16_t4 first, uint16_t4 second) {
// CHECK: %[[ADD:.+]] = add <3 x i16> %[[Shuffle]], %[[Shuffle1]]
}
+typedef unsigned _BitInt(4) uint4_t4 __attribute__((ext_vector_type(4)));
+void VectorTest(uint4_t4 first, uint4_t4 second) {
+ // LIN64: define{{.*}} void @_Z10VectorTestDv4_DU4_S0_(i32 %{{.+}}, i32
%{{.+}})
+ // LIN32: define{{.*}} void @_Z10VectorTestDv4_DU4_S0_(<4 x i4> %{{.+}}, <4
x i4> %{{.+}})
+ // WIN64: define dso_local void
@"?VectorTest@@YAXT?$__vector@U?$_UBitInt@$03@__clang@@$03@__clang@@0@Z"(<4 x
i4> %{{.+}}, <4 x i4> %{{.+}})
+ // WIN32: define dso_local void
@"?VectorTest@@YAXT?$__vector@U?$_UBitInt@$03@__clang@@$03@__clang@@0@Z"(<4 x
i4> inreg %{{.+}}, <4 x i4> inreg %{{.+}})
+ first.xzw + second.zwx;
+ // CHECK: %[[Shuffle:.+]] = shufflevector <4 x i4> %{{.+}}, <4 x i4> poison,
<3 x i32> <i32 0, i32 2, i32 3>
+ // CHECK: %[[Shuffle1:.+]] = shufflevector <4 x i4> %{{.+}}, <4 x i4>
poison, <3 x i32> <i32 2, i32 3, i32 0>
+ // CHECK: %[[ADD:.+]] = add <3 x i4> %[[Shuffle]], %[[Shuffle1]]
+}
+
+typedef unsigned _BitInt(2) uint2_t2 __attribute__((ext_vector_type(2)));
+uint2_t2 TestBitIntVector2x2Alloca(uint2_t2 v1, uint2_t2 v2) {
----------------
MrSidims wrote:
name suggests, that I had also TestBitIntVector3/4/8x2Alloca tests, but they
were not interesting, just 3 element test case brough some expected shuffles,
but it's tested elsewhere many times.
https://github.com/llvm/llvm-project/pull/140253
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