================
@@ -1777,6 +1778,35 @@ mlir::LogicalResult
CIRToLLVMVecInsertOpLowering::matchAndRewrite(
return mlir::success();
}
+mlir::LogicalResult CIRToLLVMVecCmpOpLowering::matchAndRewrite(
+ cir::VecCmpOp op, OpAdaptor adaptor,
+ mlir::ConversionPatternRewriter &rewriter) const {
+ assert(mlir::isa<cir::VectorType>(op.getType()) &&
+ mlir::isa<cir::VectorType>(op.getLhs().getType()) &&
+ mlir::isa<cir::VectorType>(op.getRhs().getType()) &&
+ "Vector compare with non-vector type");
+ // LLVM IR vector comparison returns a vector of i1. This one-bit vector
+ // must be sign-extended to the correct result type.
----------------
xlauko wrote:
Can you move this comment above creation of SExt , where it make more sense.
https://github.com/llvm/llvm-project/pull/140597
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