================ @@ -8811,6 +8820,68 @@ void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands) Inst.getOperand(ModIdx).setImm(ModVal); } } +void AMDGPUAsmParser::cvtScaledMFMA(MCInst &Inst, + const OperandVector &Operands) { + OptionalImmIndexMap OptionalIdx; + unsigned Opc = Inst.getOpcode(); + unsigned I = 1; + + const MCInstrDesc &Desc = MII.get(Opc); + + for (unsigned J = 0; J < Desc.getNumDefs(); ++J) + static_cast<AMDGPUOperand &>(*Operands[I++]).addRegOperands(Inst, 1); + + for (unsigned E = Operands.size(); I != E; ++I) { + AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands[I]); + + if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) { + Op.addRegOrImmWithFPInputModsOperands(Inst, 2); + } else if (Op.isImmModifier()) { + OptionalIdx[Op.getImmTy()] = I; + } else { + Op.addRegOrImmOperands(Inst, 1); + } + } + + // Insert CBSZ and BLGP operands for F8F6F4 variants + int InsertPos = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::cbsz); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCBSZ, + 0, InsertPos); + InsertPos = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::blgp); + addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyBLGP, + 0, InsertPos); + + // Add dummy src_modifiers + Inst.addOperand(MCOperand::createImm(0)); + Inst.addOperand(MCOperand::createImm(0)); + + // Handle op_sel fields + + unsigned OpSel = 0; + auto OpselIdx = OptionalIdx.find(AMDGPUOperand::ImmTyOpSel); + if (OpselIdx != OptionalIdx.end()) + OpSel = static_cast<const AMDGPUOperand &>(*Operands[OpselIdx->second]) + .getImm(); + + unsigned OpSelHi = 0; + auto OpselHiIdx = OptionalIdx.find(AMDGPUOperand::ImmTyOpSelHi); + if (OpselHiIdx != OptionalIdx.end()) + OpSelHi = static_cast<const AMDGPUOperand &>(*Operands[OpselHiIdx->second]) + .getImm(); + static const AMDGPU::OpName ModOps[] = {AMDGPU::OpName::src0_modifiers, + AMDGPU::OpName::src1_modifiers}; ---------------- arsenm wrote:
```suggestion const AMDGPU::OpName ModOps[] = {AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers}; ``` https://github.com/llvm/llvm-project/pull/140183 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits