https://github.com/AaronBallman created https://github.com/llvm/llvm-project/pull/144402
Reverts llvm/llvm-project#144022 This has been failing postcommit CI for two days: https://lab.llvm.org/buildbot/#/builders/63 >From d644265d459731aaf4ed38855167262d957a95eb Mon Sep 17 00:00:00 2001 From: Aaron Ballman <aa...@aaronballman.com> Date: Mon, 16 Jun 2025 13:41:58 -0400 Subject: [PATCH] Revert "[RISCV] Remove B and Zbc extension from Andes series cpus. (#144022)" This reverts commit 24c8d900c47edeefb85643a06bc32235d9f42ea3. --- .../Driver/print-enabled-extensions/riscv-andes-a25.c | 7 ++++++- .../Driver/print-enabled-extensions/riscv-andes-a45.c | 6 +++++- .../Driver/print-enabled-extensions/riscv-andes-ax25.c | 7 ++++++- .../Driver/print-enabled-extensions/riscv-andes-ax45.c | 6 +++++- .../Driver/print-enabled-extensions/riscv-andes-n45.c | 6 +++++- .../Driver/print-enabled-extensions/riscv-andes-nx45.c | 6 +++++- llvm/lib/Target/RISCV/RISCVProcessors.td | 8 ++++++++ llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s | 2 +- 8 files changed, 41 insertions(+), 7 deletions(-) diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c index cfb4d0ed58d11..d8b3848d84520 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-a25.c @@ -10,6 +10,7 @@ // CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) // CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) // CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) // CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) // CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) @@ -18,8 +19,12 @@ // CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) // CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) // CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: -// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_xandesperf5p0 +// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0 diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c index 3c3c554dffc57..a0a1c35911409 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c @@ -10,6 +10,7 @@ // CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) // CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) // CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) // CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) // CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) @@ -18,8 +19,11 @@ // CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) // CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) // CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: -// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_xandesperf5p0 +// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0 diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c index 70100a0a8df13..3f933ecd8ac83 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax25.c @@ -10,6 +10,7 @@ // CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) // CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) // CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) // CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) // CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) @@ -17,8 +18,12 @@ // CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) // CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) // CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: -// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xandesperf5p0 +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0_xandesperf5p0 diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c index d2b1a32e321e5..6460d701411bc 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c @@ -10,6 +10,7 @@ // CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) // CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) // CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) // CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) // CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) @@ -17,8 +18,11 @@ // CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) // CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) // CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: -// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xandesperf5p0 +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0 diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c index 1a2c30bfc7a2e..4d9c514b756e6 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c @@ -10,6 +10,7 @@ // CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) // CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) // CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) // CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) // CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) @@ -18,8 +19,11 @@ // CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) // CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) // CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: -// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_xandesperf5p0 +// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0 diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c index 50c38da3bd034..5eaada3f9e164 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c @@ -10,6 +10,7 @@ // CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) // CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) // CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) // CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) // CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) // CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) @@ -17,8 +18,11 @@ // CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) // CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) // CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: -// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_xandesperf5p0 +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0 diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index d7e6c71ea062e..32f4ab607a34c 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -703,6 +703,8 @@ def ANDES_A25 : RISCVProcessorModel<"andes-a25", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, + FeatureStdExtB, + FeatureStdExtZbc, FeatureVendorXAndesPerf]>; def ANDES_AX25 : RISCVProcessorModel<"andes-ax25", @@ -716,6 +718,8 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, + FeatureStdExtB, + FeatureStdExtZbc, FeatureVendorXAndesPerf]>; defvar Andes45TuneFeatures = [TuneAndes45, @@ -737,6 +741,7 @@ def ANDES_N45 : RISCVProcessorModel<"andes-n45", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, + FeatureStdExtB, FeatureVendorXAndesPerf], Andes45TuneFeatures>; @@ -751,6 +756,7 @@ def ANDES_NX45 : RISCVProcessorModel<"andes-nx45", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, + FeatureStdExtB, FeatureVendorXAndesPerf], Andes45TuneFeatures>; @@ -765,6 +771,7 @@ def ANDES_A45 : RISCVProcessorModel<"andes-a45", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, + FeatureStdExtB, FeatureVendorXAndesPerf], Andes45TuneFeatures>; @@ -779,5 +786,6 @@ def ANDES_AX45 : RISCVProcessorModel<"andes-ax45", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, + FeatureStdExtB, FeatureVendorXAndesPerf], Andes45TuneFeatures>; diff --git a/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s b/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s index d90dce8c5c3fc..f6dc6eef3f0ff 100644 --- a/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s +++ b/llvm/test/tools/llvm-mca/RISCV/Andes45/gpr.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+b,+zbc -timeline -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -mattr=+zbc -timeline -iterations=1 < %s | FileCheck %s # Two ALUs without dependency can be dispatched in the same cycle. add a0, a0, a0 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org 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