https://github.com/AditiRM created https://github.com/llvm/llvm-project/pull/144874
Support the following BCD format conversion builtins for PowerPC. - `__builtin_bcdcopysign` – Conversion that returns the decimal value of the first parameter combined with the sign code of the second parameter. - `__builtin_bcdsetsign` – Conversion that sets the sign code of the input parameter in packed decimal format. ## Prototypes ```c vector unsigned char __builtin_bcdcopysign(vector unsigned char, vector unsigned char); vector unsigned char __builtin_bcdsetsign(vector unsigned char, unsigned char); ``` ## Reference Links - [bcdcopysign](https://www.ibm.com/docs/en/xl-c-and-cpp-aix/16.1.0?topic=end-builtin-bcdcopysign-clang-based-front) - [bcdsetsign](https://www.ibm.com/docs/en/xl-c-and-cpp-aix/16.1.0?topic=end-builtin-bcdsetsign-clang-based-front) >From 8e287c19723361b0141c7bf9d1de34b145b9782c Mon Sep 17 00:00:00 2001 From: Aditi-Medhane <aditi.medh...@ibm.com> Date: Thu, 19 Jun 2025 11:04:12 +0000 Subject: [PATCH] [PowerPC] Add BCDCOPYSIGN and BCDSETSIGN Instruction Support --- clang/include/clang/Basic/BuiltinsPPC.def | 4 ++ clang/lib/Basic/Targets/PPC.cpp | 2 + clang/lib/Sema/SemaPPC.cpp | 2 + .../CodeGen/PowerPC/builtins-bcd-helpers.c | 29 ++++++++++++++ llvm/include/llvm/IR/IntrinsicsPowerPC.td | 8 ++++ llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 6 ++- .../CodeGen/PowerPC/builtins-bcd-helpers.ll | 40 +++++++++++++++++++ 7 files changed, 89 insertions(+), 2 deletions(-) create mode 100644 clang/test/CodeGen/PowerPC/builtins-bcd-helpers.c create mode 100644 llvm/test/CodeGen/PowerPC/builtins-bcd-helpers.ll diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def index bb7d54bbb793e..c3825822ce0b8 100644 --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -515,6 +515,10 @@ TARGET_BUILTIN(__builtin_altivec_vctzh, "V8UsV8Us", "", "power9-vector") TARGET_BUILTIN(__builtin_altivec_vctzw, "V4UiV4Ui", "", "power9-vector") TARGET_BUILTIN(__builtin_altivec_vctzd, "V2ULLiV2ULLi", "", "power9-vector") +//P9 BCD builtins +TARGET_BUILTIN(__builtin_ppc_bcdcopysign, "V16UcV16UcV16Uc", "", "power9-vector") +TARGET_BUILTIN(__builtin_ppc_bcdsetsign, "V16UcV16UcUc", "t", "power9-vector") + // P7 BCD builtins. TARGET_BUILTIN(__builtin_cdtbcd, "UiUi", "", "isa-v206-instructions") TARGET_BUILTIN(__builtin_cbcdtd, "UiUi", "", "isa-v206-instructions") diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp index e6ef0ecc526ba..876348c29b707 100644 --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -88,6 +88,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, } static void defineXLCompatMacros(MacroBuilder &Builder) { + Builder.defineMacro("__builtin_bcdcopysign", "__builtin_ppc_bcdcopysign"); + Builder.defineMacro("__builtin_bcdsetsign", "__builtin_ppc_bcdsetsign"); Builder.defineMacro("__cdtbcd", "__builtin_ppc_cdtbcd"); Builder.defineMacro("__cbcdtd", "__builtin_ppc_cbcdtd"); Builder.defineMacro("__addg6s", "__builtin_ppc_addg6s"); diff --git a/clang/lib/Sema/SemaPPC.cpp b/clang/lib/Sema/SemaPPC.cpp index 9b4d82745f881..71673062044af 100644 --- a/clang/lib/Sema/SemaPPC.cpp +++ b/clang/lib/Sema/SemaPPC.cpp @@ -106,6 +106,8 @@ bool SemaPPC::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, switch (BuiltinID) { default: return false; + case PPC::BI__builtin_ppc_bcdsetsign: + return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1); case PPC::BI__builtin_altivec_crypto_vshasigmaw: case PPC::BI__builtin_altivec_crypto_vshasigmad: return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1) || diff --git a/clang/test/CodeGen/PowerPC/builtins-bcd-helpers.c b/clang/test/CodeGen/PowerPC/builtins-bcd-helpers.c new file mode 100644 index 0000000000000..0aeb720e545ed --- /dev/null +++ b/clang/test/CodeGen/PowerPC/builtins-bcd-helpers.c @@ -0,0 +1,29 @@ +// NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +// REQUIRES: powerpc-registered-target +// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -O2 -target-cpu pwr9 \ +// RUN: -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -O2 -target-cpu pwr9 \ +// RUN: -emit-llvm %s -o - | FileCheck %s +// RUN: %clang_cc1 -triple powerpc-unknown-unknown -O2 -target-cpu pwr9 \ +// RUN: -emit-llvm %s -o - | FileCheck %s + +// CHECK-LABEL: test_bcdcopysign +// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdcopysign(<16 x i8> %a, <16 x i8> %b) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +vector unsigned char test_bcdcopysign(vector unsigned char a, vector unsigned char b) { + return __builtin_ppc_bcdcopysign(a, b); +} + +// CHECK-LABEL: test_bcdsetsign_imm0 +// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8> %a, i32 0) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +vector unsigned char test_bcdsetsign_imm0(vector unsigned char a) { + return __builtin_ppc_bcdsetsign(a, '\0'); +} + +// CHECK-LABEL: test_bcdsetsign_imm1 +// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8> %a, i32 1) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +vector unsigned char test_bcdsetsign_imm1(vector unsigned char a) { + return __builtin_ppc_bcdsetsign(a, '\1'); +} diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td index 84c26599b5b70..bd9d85fdaab92 100644 --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -668,6 +668,14 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". def int_ppc_addg6s: ClangBuiltin<"__builtin_addg6s">, DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + // BCD Format conversion intrinsics + def int_ppc_bcdcopysign : ClangBuiltin<"__builtin_ppc_bcdcopysign">, + DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; + def int_ppc_bcdsetsign : ClangBuiltin<"__builtin_ppc_bcdsetsign">, + DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], + [IntrNoMem, ImmArg<ArgIndex<1>>]>; + + def int_ppc_bcdadd : ClangBuiltin<"__builtin_ppc_bcdadd">, DefaultAttrsIntrinsic< [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty], diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index 386c94a324996..bf268a074496b 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -1626,9 +1626,11 @@ def BCDCTSQ_rec : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>; // Decimal Copy-Sign/Set-Sign let Defs = [CR6] in -def BCDCPSGN_rec : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", []>; +def BCDCPSGN_rec : VX1_VT5_VA5_VB5<833, "bcdcpsgn.", + [(set v16i8:$VD, (int_ppc_bcdcopysign v16i8:$VA, v16i8:$VB))]>; -def BCDSETSGN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", []>; +def BCDSETSGN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<31, 385, "bcdsetsgn.", + [(set v16i8:$VD, (int_ppc_bcdsetsign v16i8:$VB, i32:$PS))]>; // Decimal Shift/Unsigned-Shift/Shift-and-Round def BCDS_rec : VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>; diff --git a/llvm/test/CodeGen/PowerPC/builtins-bcd-helpers.ll b/llvm/test/CodeGen/PowerPC/builtins-bcd-helpers.ll new file mode 100644 index 0000000000000..ede86254b1516 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/builtins-bcd-helpers.ll @@ -0,0 +1,40 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 \ +; RUN: --ppc-asm-full-reg-names < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr9 \ +; RUN: --ppc-asm-full-reg-names < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \ +; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s + +define dso_local <16 x i8> @test_bcdcopysign(<16 x i8> noundef %a, <16 x i8> noundef %b) { +; CHECK-LABEL: test_bcdcopysign: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: bcdcpsgn. v2, v2, v3 +; CHECK-NEXT: blr +entry: + %0 = tail call <16 x i8> @llvm.ppc.bcdcopysign(<16 x i8> %a, <16 x i8> %b) + ret <16 x i8> %0 +} + +define dso_local <16 x i8> @test_bcdsetsign_imm0(<16 x i8> noundef %a) { +; CHECK-LABEL: test_bcdsetsign_imm0: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: bcdsetsgn. v2, v2, 0 +; CHECK-NEXT: blr +entry: + %0 = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8> %a, i32 0) + ret <16 x i8> %0 +} + +define dso_local <16 x i8> @test_bcdsetsign_imm1(<16 x i8> noundef %a) { +; CHECK-LABEL: test_bcdsetsign_imm1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: bcdsetsgn. v2, v2, 1 +; CHECK-NEXT: blr +entry: + %0 = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8> %a, i32 1) + ret <16 x i8> %0 +} + +declare <16 x i8> @llvm.ppc.bcdcopysign(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8>, i32) _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
