https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/151106
>From 0621311ea29b1d0b707b43e19975a5a4b67b038f Mon Sep 17 00:00:00 2001 From: Jim Lin <j...@andestech.com> Date: Wed, 11 Jun 2025 09:45:46 +0800 Subject: [PATCH 1/6] [RISCV] Implement MC support for Zvfbfa extension This patch adds MC support for Zvfbfa https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfbfa.adoc Since Zvfbfa implies Zve32f, vector floating-point instructions can be used directly with Zvfbfa extension. --- .../Driver/print-supported-extensions-riscv.c | 1 + .../test/Preprocessor/riscv-target-features.c | 9 +++++ llvm/docs/RISCVUsage.rst | 1 + llvm/docs/ReleaseNotes.md | 2 ++ .../llvm/TargetParser/RISCVTargetParser.h | 2 +- .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 27 +++++++++++---- .../RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 7 ++-- llvm/lib/Target/RISCV/RISCVFeatures.td | 19 +++++++++++ llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td | 4 +-- llvm/lib/TargetParser/RISCVTargetParser.cpp | 9 ++++- llvm/test/CodeGen/RISCV/attributes.ll | 4 +++ llvm/test/CodeGen/RISCV/features-info.ll | 1 + llvm/test/MC/RISCV/attribute-arch.s | 3 ++ llvm/test/MC/RISCV/rvv/invalid-alt.s | 8 +++++ llvm/test/MC/RISCV/rvv/vsetvl-alt.s | 33 +++++++++++++++++++ llvm/test/MC/RISCV/rvv/zvfbfmin.s | 22 ++++++++++--- llvm/test/MC/RISCV/rvv/zvfbfwma.s | 22 ++++++++++--- .../TargetParser/RISCVISAInfoTest.cpp | 1 + 18 files changed, 155 insertions(+), 20 deletions(-) create mode 100644 llvm/test/MC/RISCV/rvv/invalid-alt.s create mode 100644 llvm/test/MC/RISCV/rvv/vsetvl-alt.s diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 2503f2473d64a..fe1233a8061e9 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -212,6 +212,7 @@ // CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) // CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions) // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) +// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support) // CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography) // CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product) // CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 86085c21a95aa..15d8b18b93879 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -203,6 +203,7 @@ // CHECK-NOT: __riscv_zicfiss {{.*$}} // CHECK-NOT: __riscv_ztso {{.*$}} // CHECK-NOT: __riscv_zvbc32e {{.*$}} +// CHECK-NOT: __riscv_zvfbfa {{.*$}} // CHECK-NOT: __riscv_zvfbfmin {{.*$}} // CHECK-NOT: __riscv_zvfbfwma {{.*$}} // CHECK-NOT: __riscv_zvkgs {{.*$}} @@ -1769,6 +1770,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s // CHECK-ZTSO-EXT: __riscv_ztso 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32ifzvfbfa0p1 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFA-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64ifzvfbfa0p1 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFA-EXT %s +// CHECK-ZVFBFA-EXT: __riscv_zvfbfa 1000{{$}} + // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_zve32x_zvbc32e0p7 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 9f6ac558b6f7c..59a274b6ee49e 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -231,6 +231,7 @@ on support follow. ``Zve64x`` Supported ``Zve64f`` Supported ``Zve64d`` Supported + ``Zvfbfa`` Assembly Support ``Zvfbfmin`` Supported ``Zvfbfwma`` Supported ``Zvfh`` Supported diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 48d2ef1b4d1c5..f100199c89232 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -98,6 +98,8 @@ Changes to the PowerPC Backend Changes to the RISC-V Backend ----------------------------- +* Add support for Zvfbfa (Additional BF16 vector compute support) + Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h index 19a8af0cb9567..ca0d80d8516d4 100644 --- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h +++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h @@ -98,7 +98,7 @@ inline static bool isValidLMUL(unsigned LMUL, bool Fractional) { } LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic, - bool MaskAgnostic); + bool MaskAgnostic, bool Altfmt = false); LLVM_ABI unsigned encodeXSfmmVType(unsigned SEW, unsigned Widen, bool AltFmt); diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index a143d85f61ec2..2485f8e2da6cd 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -121,7 +121,7 @@ class RISCVAsmParser : public MCTargetAsmParser { bool parseVTypeToken(const AsmToken &Tok, VTypeState &State, unsigned &Sew, unsigned &Lmul, bool &Fractional, bool &TailAgnostic, - bool &MaskAgnostic); + bool &MaskAgnostic, bool &AltFmt); bool generateVTypeError(SMLoc ErrorLoc); bool generateXSfmmVTypeError(SMLoc ErrorLoc); @@ -2249,14 +2249,23 @@ ParseStatus RISCVAsmParser::parseJALOffset(OperandVector &Operands) { bool RISCVAsmParser::parseVTypeToken(const AsmToken &Tok, VTypeState &State, unsigned &Sew, unsigned &Lmul, bool &Fractional, bool &TailAgnostic, - bool &MaskAgnostic) { + bool &MaskAgnostic, bool &AltFmt) { if (Tok.isNot(AsmToken::Identifier)) return true; StringRef Identifier = Tok.getIdentifier(); if (State < VTypeState::SeenSew && Identifier.consume_front("e")) { - if (Identifier.getAsInteger(10, Sew)) - return true; + if (Identifier.getAsInteger(10, Sew)) { + if (Identifier == "16alt") { + AltFmt = true; + Sew = 16; + } else if (Identifier == "8alt") { + AltFmt = true; + Sew = 8; + } else { + return true; + } + } if (!RISCVVType::isValidSEW(Sew)) return true; @@ -2328,11 +2337,12 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) { bool Fractional = false; bool TailAgnostic = false; bool MaskAgnostic = false; + bool AltFmt = false; VTypeState State = VTypeState::SeenNothingYet; do { if (parseVTypeToken(getTok(), State, Sew, Lmul, Fractional, TailAgnostic, - MaskAgnostic)) { + MaskAgnostic, AltFmt)) { // The first time, errors return NoMatch rather than Failure if (State == VTypeState::SeenNothingYet) return ParseStatus::NoMatch; @@ -2358,12 +2368,17 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) { } unsigned VTypeI = - RISCVVType::encodeVTYPE(VLMUL, Sew, TailAgnostic, MaskAgnostic); + RISCVVType::encodeVTYPE(VLMUL, Sew, TailAgnostic, MaskAgnostic, AltFmt); Operands.push_back(RISCVOperand::createVType(VTypeI, S)); return ParseStatus::Success; } bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) { + if (STI->hasFeature(RISCV::FeatureStdExtZvfbfa)) + return Error( + ErrorLoc, + "operand must be " + "e[8|8alt|16|16alt|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]"); return Error( ErrorLoc, "operand must be " diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index 8c9ab8effa71b..c6782f36eb639 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -216,9 +216,12 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Imm = MI->getOperand(OpNo).getImm(); // Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx, - // or non-zero in bits 8 and above. + // , altfmt=1 without zvfbaf extension, or non-zero in bits 9 and above. if (RISCVVType::getVLMUL(Imm) == RISCVVType::VLMUL::LMUL_RESERVED || - RISCVVType::getSEW(Imm) > 64 || (Imm >> 8) != 0) { + RISCVVType::getSEW(Imm) > 64 || + (RISCVVType::isAltFmt(Imm) && + !STI.hasFeature(RISCV::FeatureStdExtZvfbfa)) || + (Imm >> 9) != 0) { O << formatImm(Imm); return; } diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 171940e149815..1453c02650d6c 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -680,12 +680,25 @@ def FeatureStdExtV [FeatureStdExtZvl128b, FeatureStdExtZve64d]>, RISCVExtensionBitmask<0, 21>; +def FeatureStdExtZvfbfa + : RISCVExperimentalExtension<0, 1, "Additional BF16 vector compute support", + [FeatureStdExtZve32f, FeatureStdExtZfbfmin]>; +def HasStdExtZvfbfa : Predicate<"Subtarget->hasStdExtZvfbfa()">, + AssemblerPredicate<(all_of FeatureStdExtZvfbfa), + "'Zvfbfa' (Additional BF16 vector compute support)">; + def FeatureStdExtZvfbfmin : RISCVExtension<1, 0, "Vector BF16 Converts", [FeatureStdExtZve32f]>; def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">, AssemblerPredicate<(all_of FeatureStdExtZvfbfmin), "'Zvfbfmin' (Vector BF16 Converts)">; +def HasStdExtZvfbfminOrZvfbfa + : Predicate<"Subtarget->hasStdExtZvfbfmin() || Subtarget->hasStdExtZvfbfa()">, + AssemblerPredicate<(any_of FeatureStdExtZvfbfmin, FeatureStdExtZvfbfa), + "'Zvfbfmin' (Vector BF16 Converts) or " + "'Zvfbfa' (Additional BF16 vector compute support)">; + def FeatureStdExtZvfbfwma : RISCVExtension<1, 0, "Vector BF16 widening mul-add", [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>; @@ -693,6 +706,12 @@ def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">, AssemblerPredicate<(all_of FeatureStdExtZvfbfwma), "'Zvfbfwma' (Vector BF16 widening mul-add)">; +def HasStdExtZvfbfwmaOrZvfbfa + : Predicate<"Subtarget->hasStdExtZvfbfwma() || Subtarget->hasStdExtZvfbfa()">, + AssemblerPredicate<(any_of FeatureStdExtZvfbfwma, FeatureStdExtZvfbfa), + "'Zvfbfwma' (Vector BF16 widening mul-add) or " + "'Zvfbfa' (Additional BF16 vector compute support)">; + def FeatureStdExtZvfhmin : RISCVExtension<1, 0, "Vector Half-Precision Floating-Point Minimal", diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td index cbeec9ba75f16..0aacdb3ce0c47 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td @@ -17,7 +17,7 @@ // Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtZvfbfmin], Constraints = "@earlyclobber $vd", +let Predicates = [HasStdExtZvfbfminOrZvfbfa], Constraints = "@earlyclobber $vd", mayRaiseFPException = true in { let RVVConstraint = WidenCvt, DestEEW = EEWSEWx2 in defm VFWCVTBF16_F_F_V : VWCVTF_FV_VS2<"vfwcvtbf16.f.f.v", 0b010010, 0b01101>; @@ -25,7 +25,7 @@ let Uses = [FRM, VL, VTYPE] in defm VFNCVTBF16_F_F_W : VNCVTF_FV_VS2<"vfncvtbf16.f.f.w", 0b010010, 0b11101>; } -let Predicates = [HasStdExtZvfbfwma], +let Predicates = [HasStdExtZvfbfwmaOrZvfbfa], Constraints = "@earlyclobber $vd_wb, $vd = $vd_wb", RVVConstraint = WidenV, Uses = [FRM, VL, VTYPE], mayRaiseFPException = true, DestEEW = EEWSEWx2 in { diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp index 9957ec0c28d88..c966e53321140 100644 --- a/llvm/lib/TargetParser/RISCVTargetParser.cpp +++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -153,12 +153,13 @@ namespace RISCVVType { // // Bits | Name | Description // -----+------------+------------------------------------------------ +// 8 | altfmt | Alternative format for bf16 // 7 | vma | Vector mask agnostic // 6 | vta | Vector tail agnostic // 5:3 | vsew[2:0] | Standard element width (SEW) setting // 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting unsigned encodeVTYPE(VLMUL VLMul, unsigned SEW, bool TailAgnostic, - bool MaskAgnostic) { + bool MaskAgnostic, bool Altfmt) { assert(isValidSEW(SEW) && "Invalid SEW"); unsigned VLMulBits = static_cast<unsigned>(VLMul); unsigned VSEWBits = encodeSEW(SEW); @@ -167,6 +168,8 @@ unsigned encodeVTYPE(VLMUL VLMul, unsigned SEW, bool TailAgnostic, VTypeI |= 0x40; if (MaskAgnostic) VTypeI |= 0x80; + if (Altfmt) + VTypeI |= 0x100; return VTypeI; } @@ -200,6 +203,10 @@ void printVType(unsigned VType, raw_ostream &OS) { unsigned Sew = getSEW(VType); OS << "e" << Sew; + bool AltFmt = RISCVVType::isAltFmt(VType); + if (AltFmt) + OS << "alt"; + unsigned LMul; bool Fractional; std::tie(LMul, Fractional) = decodeVLMUL(getVLMUL(VType)); diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index a28b818b3db11..c10f0c5869928 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -159,6 +159,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s ; RUN: llc -mtriple=riscv32 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV32SMRNMI %s ; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFA %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s ; RUN: llc -mtriple=riscv32 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s @@ -323,6 +324,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s ; RUN: llc -mtriple=riscv64 -mattr=+smrnmi %s -o - | FileCheck --check-prefixes=CHECK,RV64SMRNMI %s ; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFA %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s ; RUN: llc -mtriple=riscv64 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s @@ -517,6 +519,7 @@ ; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0" ; RV32SMRNMI: .attribute 5, "rv32i2p1_smrnmi1p0" ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" +; RV32ZVFBFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0" ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" ; RV32ZACAS: .attribute 5, "rv32i2p1_zaamo1p0_zacas1p0" @@ -679,6 +682,7 @@ ; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0" ; RV64SMRNMI: .attribute 5, "rv64i2p1_smrnmi1p0" ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0" +; RV64ZVFBFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0" ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" ; RV64ZACAS: .attribute 5, "rv64i2p1_zaamo1p0_zacas1p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index b94665b718ae7..07c18659836ce 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -49,6 +49,7 @@ ; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad). ; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack). ; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements). +; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support). ; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography). ; CHECK-NEXT: experimental-zvqdotq - 'Zvqdotq' (Vector quad widening 4D Dot Product). ; CHECK-NEXT: f - 'F' (Single-Precision Floating-Point). diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 19cc4d5ba1675..aa6f4c5e88325 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -405,6 +405,9 @@ .attribute arch, "rv32i_zfbfmin1p0" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0" +.attribute arch, "rv32i_zvfbfa0p1" +# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0" + .attribute arch, "rv32i_zvfbfmin1p0" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" diff --git a/llvm/test/MC/RISCV/rvv/invalid-alt.s b/llvm/test/MC/RISCV/rvv/invalid-alt.s new file mode 100644 index 0000000000000..362bcb38aabb0 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/invalid-alt.s @@ -0,0 +1,8 @@ +# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-zvfbfa --mattr=+f %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR + +vsetvli a2, a0, e32alt, m1, ta, ma +# CHECK-ERROR: operand must be e[8|8alt|16|16alt|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] + +vsetvli a2, a0, e64alt, m1, ta, ma +# CHECK-ERROR: operand must be e[8|8alt|16|16alt|32|64],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu] diff --git a/llvm/test/MC/RISCV/rvv/vsetvl-alt.s b/llvm/test/MC/RISCV/rvv/vsetvl-alt.s new file mode 100644 index 0000000000000..f4de08d762789 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/vsetvl-alt.s @@ -0,0 +1,33 @@ +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zvfbfa %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvfbfa %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-zvfbfa --no-print-imm-hex - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvfbfa %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vsetvli a2, a0, e8alt, m1, ta, ma +# CHECK-INST: vsetvli a2, a0, e8alt, m1, ta, ma +# CHECK-ENCODING: [0x57,0x76,0x05,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-UNKNOWN: 1c057657 <unknown> + +vsetvli a2, a0, e16alt, m1, ta, ma +# CHECK-INST: vsetvli a2, a0, e16alt, m1, ta, ma +# CHECK-ENCODING: [0x57,0x76,0x85,0x1c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-UNKNOWN: 1c857657 <unknown> + +vsetivli a2, 0, e8alt, m1, ta, ma +# CHECK-INST: vsetivli a2, 0, e8alt, m1, ta, ma +# CHECK-ENCODING: [0x57,0x76,0x00,0xdc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-UNKNOWN: dc007657 <unknown> + +vsetivli a2, 0, e16alt, m1, ta, ma +# CHECK-INST: vsetivli a2, 0, e16alt, m1, ta, ma +# CHECK-ENCODING: [0x57,0x76,0x80,0xdc] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} +# CHECK-UNKNOWN: dc807657 <unknown> diff --git a/llvm/test/MC/RISCV/rvv/zvfbfmin.s b/llvm/test/MC/RISCV/rvv/zvfbfmin.s index c5f05c6be0df9..9e7889979c712 100644 --- a/llvm/test/MC/RISCV/rvv/zvfbfmin.s +++ b/llvm/test/MC/RISCV/rvv/zvfbfmin.s @@ -1,42 +1,56 @@ # RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+zvfbfmin %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+experimental-zvfbfa %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR # RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+zvfbfmin %s \ # RUN: | llvm-objdump -d --mattr=+zvfbfmin - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfbfa %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-zvfbfa - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST # RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+zvfbfmin %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfbfa %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN # RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+zvfbfmin %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+experimental-zvfbfa %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR # RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+zvfbfmin %s \ # RUN: | llvm-objdump -d --mattr=+zvfbfmin - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfbfa %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-zvfbfa - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST # RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+zvfbfmin %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfbfa %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN # CHECK-INST: vfncvtbf16.f.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x4e,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} # CHECK-UNKNOWN: 484e9457 <unknown> vfncvtbf16.f.f.w v8, v4, v0.t # CHECK-INST: vfncvtbf16.f.f.w v8, v4 # CHECK-ENCODING: [0x57,0x94,0x4e,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} # CHECK-UNKNOWN: 4a4e9457 <unknown> vfncvtbf16.f.f.w v8, v4 # CHECK-INST: vfwcvtbf16.f.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x46,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} # CHECK-UNKNOWN: 48469457 <unknown> vfwcvtbf16.f.f.v v8, v4, v0.t # CHECK-INST: vfwcvtbf16.f.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x46,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} # CHECK-UNKNOWN: 4a469457 <unknown> vfwcvtbf16.f.f.v v8, v4 diff --git a/llvm/test/MC/RISCV/rvv/zvfbfwma.s b/llvm/test/MC/RISCV/rvv/zvfbfwma.s index 3ba5d38aacccd..45334fee1572c 100644 --- a/llvm/test/MC/RISCV/rvv/zvfbfwma.s +++ b/llvm/test/MC/RISCV/rvv/zvfbfwma.s @@ -1,43 +1,57 @@ # RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+zvfbfwma %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+experimental-zvfbfa %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR # RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+zvfbfwma %s \ # RUN: | llvm-objdump -d --mattr=+zvfbfwma --no-print-imm-hex - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfbfa %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-zvfbfa --no-print-imm-hex - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST # RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+zvfbfwma %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfbfa %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN # RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+zvfbfwma %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+experimental-zvfbfa %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR # RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+zvfbfwma %s \ # RUN: | llvm-objdump -d --mattr=+zvfbfwma --no-print-imm-hex - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfbfa %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-zvfbfa --no-print-imm-hex - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST # RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+zvfbfwma %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfbfa %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN # CHECK-INST: vfwmaccbf16.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xec] -# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} # CHECK-UNKNOWN: ec4a1457 <unknown> vfwmaccbf16.vv v8, v20, v4, v0.t # CHECK-INST: vfwmaccbf16.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xee] -# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} # CHECK-UNKNOWN: ee4a1457 <unknown> vfwmaccbf16.vv v8, v20, v4 # CHECK-INST: vfwmaccbf16.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xec] -# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} # CHECK-UNKNOWN: ec455457 <unknown> vfwmaccbf16.vf v8, fa0, v4, v0.t # CHECK-INST: vfwmaccbf16.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xee] -# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} # CHECK-UNKNOWN: ee455457 <unknown> vfwmaccbf16.vf v8, fa0, v4 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 319538eaea135..1f40bdc0471d9 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1183,6 +1183,7 @@ Experimental extensions zicfiss 1.0 zalasr 0.1 zvbc32e 0.7 + zvfbfa 0.1 zvkgs 0.7 zvqdotq 0.0 smctr 1.0 >From 207bfb3852dae35e5e2a054e637939d2ce15dc29 Mon Sep 17 00:00:00 2001 From: Jim Lin <j...@andestech.com> Date: Wed, 30 Jul 2025 09:50:42 +0800 Subject: [PATCH 2/6] Remove the instructions that belong to Zvfbfmin and Zvfbfwma from Zvfbfa --- llvm/lib/Target/RISCV/RISCVFeatures.td | 12 ----------- llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td | 4 ++-- llvm/test/MC/RISCV/rvv/zvfbfmin.s | 22 ++++---------------- llvm/test/MC/RISCV/rvv/zvfbfwma.s | 22 ++++---------------- 4 files changed, 10 insertions(+), 50 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 1453c02650d6c..b9b7e42546411 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -693,12 +693,6 @@ def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">, AssemblerPredicate<(all_of FeatureStdExtZvfbfmin), "'Zvfbfmin' (Vector BF16 Converts)">; -def HasStdExtZvfbfminOrZvfbfa - : Predicate<"Subtarget->hasStdExtZvfbfmin() || Subtarget->hasStdExtZvfbfa()">, - AssemblerPredicate<(any_of FeatureStdExtZvfbfmin, FeatureStdExtZvfbfa), - "'Zvfbfmin' (Vector BF16 Converts) or " - "'Zvfbfa' (Additional BF16 vector compute support)">; - def FeatureStdExtZvfbfwma : RISCVExtension<1, 0, "Vector BF16 widening mul-add", [FeatureStdExtZvfbfmin, FeatureStdExtZfbfmin]>; @@ -706,12 +700,6 @@ def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">, AssemblerPredicate<(all_of FeatureStdExtZvfbfwma), "'Zvfbfwma' (Vector BF16 widening mul-add)">; -def HasStdExtZvfbfwmaOrZvfbfa - : Predicate<"Subtarget->hasStdExtZvfbfwma() || Subtarget->hasStdExtZvfbfa()">, - AssemblerPredicate<(any_of FeatureStdExtZvfbfwma, FeatureStdExtZvfbfa), - "'Zvfbfwma' (Vector BF16 widening mul-add) or " - "'Zvfbfa' (Additional BF16 vector compute support)">; - def FeatureStdExtZvfhmin : RISCVExtension<1, 0, "Vector Half-Precision Floating-Point Minimal", diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td index 0aacdb3ce0c47..cbeec9ba75f16 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td @@ -17,7 +17,7 @@ // Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtZvfbfminOrZvfbfa], Constraints = "@earlyclobber $vd", +let Predicates = [HasStdExtZvfbfmin], Constraints = "@earlyclobber $vd", mayRaiseFPException = true in { let RVVConstraint = WidenCvt, DestEEW = EEWSEWx2 in defm VFWCVTBF16_F_F_V : VWCVTF_FV_VS2<"vfwcvtbf16.f.f.v", 0b010010, 0b01101>; @@ -25,7 +25,7 @@ let Uses = [FRM, VL, VTYPE] in defm VFNCVTBF16_F_F_W : VNCVTF_FV_VS2<"vfncvtbf16.f.f.w", 0b010010, 0b11101>; } -let Predicates = [HasStdExtZvfbfwmaOrZvfbfa], +let Predicates = [HasStdExtZvfbfwma], Constraints = "@earlyclobber $vd_wb, $vd = $vd_wb", RVVConstraint = WidenV, Uses = [FRM, VL, VTYPE], mayRaiseFPException = true, DestEEW = EEWSEWx2 in { diff --git a/llvm/test/MC/RISCV/rvv/zvfbfmin.s b/llvm/test/MC/RISCV/rvv/zvfbfmin.s index 9e7889979c712..c5f05c6be0df9 100644 --- a/llvm/test/MC/RISCV/rvv/zvfbfmin.s +++ b/llvm/test/MC/RISCV/rvv/zvfbfmin.s @@ -1,56 +1,42 @@ # RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+zvfbfmin %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+experimental-zvfbfa %s \ -# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR # RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+zvfbfmin %s \ # RUN: | llvm-objdump -d --mattr=+zvfbfmin - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfbfa %s \ -# RUN: | llvm-objdump -d --mattr=+experimental-zvfbfa - \ -# RUN: | FileCheck %s --check-prefix=CHECK-INST # RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+zvfbfmin %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfbfa %s \ -# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN # RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+zvfbfmin %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+experimental-zvfbfa %s \ -# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR # RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+zvfbfmin %s \ # RUN: | llvm-objdump -d --mattr=+zvfbfmin - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfbfa %s \ -# RUN: | llvm-objdump -d --mattr=+experimental-zvfbfa - \ -# RUN: | FileCheck %s --check-prefix=CHECK-INST # RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+zvfbfmin %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfbfa %s \ -# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN # CHECK-INST: vfncvtbf16.f.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x4e,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} # CHECK-UNKNOWN: 484e9457 <unknown> vfncvtbf16.f.f.w v8, v4, v0.t # CHECK-INST: vfncvtbf16.f.f.w v8, v4 # CHECK-ENCODING: [0x57,0x94,0x4e,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} # CHECK-UNKNOWN: 4a4e9457 <unknown> vfncvtbf16.f.f.w v8, v4 # CHECK-INST: vfwcvtbf16.f.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x46,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} # CHECK-UNKNOWN: 48469457 <unknown> vfwcvtbf16.f.f.v v8, v4, v0.t # CHECK-INST: vfwcvtbf16.f.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x46,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} # CHECK-UNKNOWN: 4a469457 <unknown> vfwcvtbf16.f.f.v v8, v4 diff --git a/llvm/test/MC/RISCV/rvv/zvfbfwma.s b/llvm/test/MC/RISCV/rvv/zvfbfwma.s index 45334fee1572c..3ba5d38aacccd 100644 --- a/llvm/test/MC/RISCV/rvv/zvfbfwma.s +++ b/llvm/test/MC/RISCV/rvv/zvfbfwma.s @@ -1,57 +1,43 @@ # RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+zvfbfwma %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+experimental-zvfbfa %s \ -# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR # RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+zvfbfwma %s \ # RUN: | llvm-objdump -d --mattr=+zvfbfwma --no-print-imm-hex - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfbfa %s \ -# RUN: | llvm-objdump -d --mattr=+experimental-zvfbfa --no-print-imm-hex - \ -# RUN: | FileCheck %s --check-prefix=CHECK-INST # RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+zvfbfwma %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfbfa %s \ -# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN # RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+zvfbfwma %s \ # RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+experimental-zvfbfa %s \ -# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST # RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR # RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+zvfbfwma %s \ # RUN: | llvm-objdump -d --mattr=+zvfbfwma --no-print-imm-hex - \ # RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfbfa %s \ -# RUN: | llvm-objdump -d --mattr=+experimental-zvfbfa --no-print-imm-hex - \ -# RUN: | FileCheck %s --check-prefix=CHECK-INST # RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+zvfbfwma %s \ # RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN -# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfbfa %s \ -# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN # CHECK-INST: vfwmaccbf16.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xec] -# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} # CHECK-UNKNOWN: ec4a1457 <unknown> vfwmaccbf16.vv v8, v20, v4, v0.t # CHECK-INST: vfwmaccbf16.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xee] -# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} # CHECK-UNKNOWN: ee4a1457 <unknown> vfwmaccbf16.vv v8, v20, v4 # CHECK-INST: vfwmaccbf16.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xec] -# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} # CHECK-UNKNOWN: ec455457 <unknown> vfwmaccbf16.vf v8, fa0, v4, v0.t # CHECK-INST: vfwmaccbf16.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xee] -# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add) or 'Zvfbfa' (Additional BF16 vector compute support){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} # CHECK-UNKNOWN: ee455457 <unknown> vfwmaccbf16.vf v8, fa0, v4 >From d0ba417df5f933dab3d426156f6369acbe742f13 Mon Sep 17 00:00:00 2001 From: Jim Lin <j...@andestech.com> Date: Wed, 30 Jul 2025 09:52:37 +0800 Subject: [PATCH 3/6] Adjust the comment --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index c6782f36eb639..40e10d7e4c432 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -216,7 +216,7 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Imm = MI->getOperand(OpNo).getImm(); // Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx, - // , altfmt=1 without zvfbaf extension, or non-zero in bits 9 and above. + // altfmt=1 without zvfbfa extension, or non-zero in bits 9 and above. if (RISCVVType::getVLMUL(Imm) == RISCVVType::VLMUL::LMUL_RESERVED || RISCVVType::getSEW(Imm) > 64 || (RISCVVType::isAltFmt(Imm) && >From 5347b092e91cc6403506cf08d2f5a481cbc5fc7d Mon Sep 17 00:00:00 2001 From: Jim Lin <j...@andestech.com> Date: Wed, 30 Jul 2025 09:54:42 +0800 Subject: [PATCH 4/6] Altfmt -> AltFmt --- llvm/lib/TargetParser/RISCVTargetParser.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp index c966e53321140..3a9239e49b8e8 100644 --- a/llvm/lib/TargetParser/RISCVTargetParser.cpp +++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -159,7 +159,7 @@ namespace RISCVVType { // 5:3 | vsew[2:0] | Standard element width (SEW) setting // 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting unsigned encodeVTYPE(VLMUL VLMul, unsigned SEW, bool TailAgnostic, - bool MaskAgnostic, bool Altfmt) { + bool MaskAgnostic, bool AltFmt) { assert(isValidSEW(SEW) && "Invalid SEW"); unsigned VLMulBits = static_cast<unsigned>(VLMul); unsigned VSEWBits = encodeSEW(SEW); >From 896496b5176509fbee9568e1ed8435a0e3189af1 Mon Sep 17 00:00:00 2001 From: Jim Lin <j...@andestech.com> Date: Wed, 30 Jul 2025 09:57:41 +0800 Subject: [PATCH 5/6] Altfmt -> AltFmt --- llvm/include/llvm/TargetParser/RISCVTargetParser.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h index ca0d80d8516d4..b1fca55a5afcd 100644 --- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h +++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h @@ -98,7 +98,7 @@ inline static bool isValidLMUL(unsigned LMUL, bool Fractional) { } LLVM_ABI unsigned encodeVTYPE(VLMUL VLMUL, unsigned SEW, bool TailAgnostic, - bool MaskAgnostic, bool Altfmt = false); + bool MaskAgnostic, bool AltFmt = false); LLVM_ABI unsigned encodeXSfmmVType(unsigned SEW, unsigned Widen, bool AltFmt); >From 10ffa9cfe37a153dfc44b6801181a20e3fef9336 Mon Sep 17 00:00:00 2001 From: Jim Lin <j...@andestech.com> Date: Wed, 30 Jul 2025 10:03:27 +0800 Subject: [PATCH 6/6] Altfmt -> AltFmt --- llvm/lib/TargetParser/RISCVTargetParser.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp index 3a9239e49b8e8..b53a1b95431aa 100644 --- a/llvm/lib/TargetParser/RISCVTargetParser.cpp +++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -168,7 +168,7 @@ unsigned encodeVTYPE(VLMUL VLMul, unsigned SEW, bool TailAgnostic, VTypeI |= 0x40; if (MaskAgnostic) VTypeI |= 0x80; - if (Altfmt) + if (AltFmt) VTypeI |= 0x100; return VTypeI; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
