Author: Venkata Ramanaiah Nalamothu Date: 2025-07-31T21:31:23+05:30 New Revision: 523b4b0312ccd76d3a94e9b43779b2f6b932c43d
URL: https://github.com/llvm/llvm-project/commit/523b4b0312ccd76d3a94e9b43779b2f6b932c43d DIFF: https://github.com/llvm/llvm-project/commit/523b4b0312ccd76d3a94e9b43779b2f6b932c43d.diff LOG: [Docs] Fix typo in shadow call stack option name (#151474) Fix typo in shadow call stack option name mentioned in 'ShadowCallStack.rst'. Added: Modified: clang/docs/ShadowCallStack.rst Removed: ################################################################################ diff --git a/clang/docs/ShadowCallStack.rst b/clang/docs/ShadowCallStack.rst index fc8bea83e1145..9b104cc3b7180 100644 --- a/clang/docs/ShadowCallStack.rst +++ b/clang/docs/ShadowCallStack.rst @@ -61,7 +61,7 @@ The instrumentation makes use of the platform register ``x18`` on AArch64, ``x3`` (``gp``) on RISC-V with software shadow stack and ``ssp`` on RISC-V with hardware shadow stack, which needs `Zicfiss`_ and ``-fcf-protection=return``. Users can choose between the software and hardware based shadow stack -implementation on RISC-V backend by passing ``-fsanitize=shadowcallstack`` +implementation on RISC-V backend by passing ``-fsanitize=shadow-call-stack`` or ``Zicfiss`` with ``-fcf-protection=return``. For simplicity we will refer to this as the ``SCSReg``. On some platforms, ``SCSReg`` is reserved, and on others, it is designated as a scratch register. _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
