================ @@ -787,6 +787,9 @@ def VR : VReg<!listconcat(VM1VTs, VMaskVTs), def VRNoV0 : VReg<!listconcat(VM1VTs, VMaskVTs), (sub VR, V0), 1>; +let GeneratePressureSet = false in +def VREven : VReg<!listconcat(VM1VTs, VMaskVTs), ---------------- link-xyq wrote:
This VREven only constrains a single even-indexed register (e.g., v2) and cannot semantically represent the occupation of two registers, which misaligns with the instruction behavior. When adding intrinsic support in the future, we will explicitly address this limitation. https://github.com/llvm/llvm-project/pull/151706 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
