https://github.com/aadeshps-mcw updated
https://github.com/llvm/llvm-project/pull/153549
>From ef9d20bdcdac96043893ac9078e6e152d540d88f Mon Sep 17 00:00:00 2001
From: Aadesh PremKumar <aadesh.premku...@multicorewareinc.com>
Date: Thu, 14 Aug 2025 10:45:13 +0530
Subject: [PATCH 1/2] --Added test for
SPV_INTEL_device_side_avc_motion_estimation,
--SPV_INTEL_fast_math_mode,SPV_KHR_bfloat16,SPV_KHR_untyped_pointers
extensions. --These are marked as Xfail, because they are not yet implemented
---
.../subgroup_avc_intel_generic.cl | 152 ++++++++++++++++++
.../subgroup_avc_intel_not_builtin.ll.ll | 12 ++
.../subgroup_avc_intel_types.ll | 48 ++++++
.../subgroup_avc_intel_wrappers.ll.ll | 86 ++++++++++
.../fp_contract_reassoc_fast_mode.ll | 35 ++++
.../extensions/SPV_KHR_bfloat16/bfloat16.ll | 20 +++
.../SPV_KHR_bfloat16/bfloat16_dot.ll | 22 +++
.../cooperative_matrix_bfloat16.ll | 25 +++
.../SPV_KHR_untyped_pointers/globals.ll | 48 ++++++
.../SPV_KHR_untyped_pointers/infinite-phi.ll | 35 ++++
.../SPV_KHR_untyped_pointers/read_image.ll | 51 ++++++
.../SPV_KHR_untyped_pointers/store.ll | 47 ++++++
.../untyped_ptr_access_chain.ll | 26 +++
.../untyped_ptr_type.ll | 24 +++
14 files changed, 631 insertions(+)
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_not_builtin.ll.ll
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_types.ll
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_wrappers.ll.ll
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fast_math_mode/fp_contract_reassoc_fast_mode.ll
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16.ll
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16_dot.ll
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/cooperative_matrix_bfloat16.ll
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/globals.ll
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/infinite-phi.ll
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/read_image.ll
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/store.ll
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/untyped_ptr_access_chain.ll
create mode 100644
llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/untyped_ptr_type.ll
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl
b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl
new file mode 100644
index 0000000000000..5dc1c98f23ac1
--- /dev/null
+++
b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl
@@ -0,0 +1,152 @@
+; RUN: clang -cc1 -O1 -triple spirv64-unknown-unknown -cl-std=CL2.0
-finclude-default-header -emit-llvm %s -o %t.ll
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_INTEL_device_side_avc_motion_estimation %t.ll -o - | FileCheck
%s
+; XFAIL: *
+
+void foo(intel_sub_group_avc_ime_payload_t ime_payload,
+ intel_sub_group_avc_ime_result_single_reference_streamout_t sstreamout,
+ intel_sub_group_avc_ime_result_dual_reference_streamout_t dstreamout,
+ intel_sub_group_avc_ime_result_t ime_result,
+ intel_sub_group_avc_mce_result_t mce_result,
+ intel_sub_group_avc_ref_payload_t ref_payload,
+ intel_sub_group_avc_sic_payload_t sic_payload,
+ intel_sub_group_avc_sic_result_t sic_result,
+ intel_sub_group_avc_mce_payload_t mce_payload) {
+ intel_sub_group_avc_mce_get_default_inter_base_multi_reference_penalty(0, 0);
+ intel_sub_group_avc_mce_get_default_inter_shape_penalty(0, 0);
+ intel_sub_group_avc_mce_get_default_intra_luma_shape_penalty(0, 0);
+ intel_sub_group_avc_mce_get_default_inter_motion_vector_cost_table(0, 0);
+ intel_sub_group_avc_mce_get_default_inter_direction_penalty(0, 0);
+ intel_sub_group_avc_mce_get_default_intra_luma_mode_penalty(0, 0);
+
+ intel_sub_group_avc_ime_initialize(0, 0, 0);
+ intel_sub_group_avc_ime_set_single_reference(0, 0, ime_payload);
+ intel_sub_group_avc_ime_set_dual_reference(0, 0, 0, ime_payload);
+ intel_sub_group_avc_ime_ref_window_size(0, 0);
+ intel_sub_group_avc_ime_ref_window_size(0, 0);
+ intel_sub_group_avc_ime_adjust_ref_offset(0, 0, 0, 0);
+ intel_sub_group_avc_ime_set_max_motion_vector_count(0, ime_payload);
+
+ intel_sub_group_avc_ime_get_single_reference_streamin(sstreamout);
+ intel_sub_group_avc_ime_get_dual_reference_streamin(dstreamout);
+ intel_sub_group_avc_ime_get_border_reached(0i, ime_result);
+ intel_sub_group_avc_ime_get_streamout_major_shape_distortions(sstreamout, 0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_distortions(dstreamout, 0,
0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_motion_vectors(sstreamout,
0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_motion_vectors(dstreamout,
0, 0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_reference_ids(sstreamout,
0);
+ intel_sub_group_avc_ime_get_streamout_major_shape_reference_ids(dstreamout,
0, 0);
+
+ intel_sub_group_avc_ime_set_dual_reference(0, 0, 0, ime_payload);
+ intel_sub_group_avc_ime_set_weighted_sad(0, ime_payload);
+ intel_sub_group_avc_ime_set_early_search_termination_threshold(0,
ime_payload);
+
+ intel_sub_group_avc_fme_initialize(0, 0, 0, 0, 0, 0, 0);
+ intel_sub_group_avc_bme_initialize(0, 0, 0, 0, 0, 0, 0, 0);
+ intel_sub_group_avc_ref_set_bidirectional_mix_disable(ref_payload);
+
+ intel_sub_group_avc_sic_initialize(0);
+ intel_sub_group_avc_sic_configure_ipe(0, 0, 0, 0, 0, 0, 0, sic_payload);
+ intel_sub_group_avc_sic_configure_ipe(0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
sic_payload);
+ intel_sub_group_avc_sic_configure_skc(0, 0, 0, 0, 0, sic_payload);
+ intel_sub_group_avc_sic_set_skc_forward_transform_enable(0, sic_payload);
+ intel_sub_group_avc_sic_set_block_based_raw_skip_sad(0, sic_payload);
+ intel_sub_group_avc_sic_set_intra_luma_shape_penalty(0, sic_payload);
+ intel_sub_group_avc_sic_set_intra_luma_mode_cost_function(0, 0, 0,
+ sic_payload);
+ intel_sub_group_avc_sic_set_intra_chroma_mode_cost_function(0, sic_payload);
+ intel_sub_group_avc_sic_get_best_ipe_luma_distortion(sic_result);
+ intel_sub_group_avc_sic_get_motion_vector_mask(0, 0);
+
+ intel_sub_group_avc_mce_set_source_interlaced_field_polarity(0, mce_payload);
+ intel_sub_group_avc_mce_set_single_reference_interlaced_field_polarity(
+ 0, mce_payload);
+ intel_sub_group_avc_mce_set_dual_reference_interlaced_field_polarities(
+ 0, 0, mce_payload);
+ intel_sub_group_avc_mce_set_inter_base_multi_reference_penalty(0,
+ mce_payload);
+ intel_sub_group_avc_mce_set_inter_shape_penalty(0, mce_payload);
+ intel_sub_group_avc_mce_set_inter_direction_penalty(0, mce_payload);
+ intel_sub_group_avc_mce_set_motion_vector_cost_function(0, 0, 0,
mce_payload);
+ intel_sub_group_avc_mce_get_inter_reference_interlaced_field_polarities(
+ 0, 0, mce_result);
+}
+
+CHECK-DAG: OpCapability Groups
+CHECK-DAG: OpCapability SubgroupAvcMotionEstimationINTEL
+CHECK-DAG: OpCapability SubgroupAvcMotionEstimationIntraINTEL
+CHECK-DAG: OpCapability SubgroupAvcMotionEstimationChromaINTEL
+CHECK-DAG: OpExtension "SPV_INTEL_device_side_avc_motion_estimation"
+
+CHECK: %[[#ImePayloadTy:]] = OpTypeAvcImePayloadINTEL
+CHECK: %[[#ImeSRefOutTy:]] = OpTypeAvcImeResultSingleReferenceStreamoutINTEL
+CHECK: %[[#ImeDRefOutTy:]] = OpTypeAvcImeResultDualReferenceStreamoutINTEL
+CHECK: %[[#ImeResultTy:]] = OpTypeAvcImeResultINTEL
+CHECK: %[[#MceResultTy:]] = OpTypeAvcMceResultINTEL
+CHECK: %[[#RefPayloadTy:]] = OpTypeAvcRefPayloadINTEL
+CHECK: %[[#SicPayloadTy:]] = OpTypeAvcSicPayloadINTEL
+CHECK: %[[#SicResultTy:]] = OpTypeAvcSicResultINTEL
+CHECK: %[[#McePayloadTy:]] = OpTypeAvcMcePayloadINTEL
+CHECK: %[[#ImeSRefInTy:]] = OpTypeAvcImeSingleReferenceStreaminINTEL
+CHECK: %[[#ImeDRefInTy:]] = OpTypeAvcImeDualReferenceStreaminINTEL
+
+CHECK: %[[#ImePayload:]] = OpFunctionParameter %[[#ImePayloadTy]]
+CHECK: %[[#ImeSRefOut:]] = OpFunctionParameter %[[#ImeSRefOutTy]]
+CHECK: %[[#ImeDRefOut:]] = OpFunctionParameter %[[#ImeDRefOutTy]]
+CHECK: %[[#ImeResult:]] = OpFunctionParameter %[[#ImeResultTy]]
+CHECK: %[[#MceResult:]] = OpFunctionParameter %[[#MceResultTy]]
+CHECK: %[[#RefPayload:]] = OpFunctionParameter %[[#RefPayloadTy]]
+CHECK: %[[#SicPayload:]] = OpFunctionParameter %[[#SicPayloadTy]]
+CHECK: %[[#SicResult:]] = OpFunctionParameter %[[#SicResultTy]]
+CHECK: %[[#McePayload:]] = OpFunctionParameter %[[#McePayloadTy]]
+
+CHECK: OpSubgroupAvcMceGetDefaultInterBaseMultiReferencePenaltyINTEL
+CHECK: OpSubgroupAvcMceGetDefaultInterShapePenaltyINTEL
+CHECK: OpSubgroupAvcMceGetDefaultIntraLumaShapePenaltyINTEL
+CHECK: OpSubgroupAvcMceGetDefaultInterMotionVectorCostTableINTEL
+CHECK: OpSubgroupAvcMceGetDefaultInterDirectionPenaltyINTEL
+CHECK: OpSubgroupAvcMceGetDefaultIntraLumaModePenaltyINTEL
+
+CHECK: OpSubgroupAvcImeInitializeINTEL %[[#ImePayloadTy]]
+CHECK: OpSubgroupAvcImeSetSingleReferenceINTEL %[[#ImePayloadTy]] {{.*}}
%[[#ImePayload]]
+CHECK: OpSubgroupAvcImeSetDualReferenceINTEL %[[#ImePayloadTy]] {{.*}}
%[[#ImePayload]]
+CHECK: OpSubgroupAvcImeRefWindowSizeINTEL
+CHECK: OpSubgroupAvcImeRefWindowSizeINTEL
+CHECK: OpSubgroupAvcImeAdjustRefOffsetINTEL
+CHECK: OpSubgroupAvcImeSetMaxMotionVectorCountINTEL %[[#ImePayloadTy]] {{.*}}
%[[#ImePayload]]
+CHECK: OpSubgroupAvcImeGetSingleReferenceStreaminINTEL
%[[#ImeSRefInTy]]{{.*}}%[[#ImeSRefOut]]
+CHECK: OpSubgroupAvcImeGetDualReferenceStreaminINTEL
%[[#ImeDRefInTy]]{{.*}}%[[#ImeDRefOut]]
+CHECK: OpSubgroupAvcImeGetBorderReachedINTEL {{.*}} %[[#ImeResult]]
+CHECK: OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeDistortionsINTEL
{{.*}} %[[#ImeSRefOut]]
+CHECK: OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeDistortionsINTEL
{{.*}} %[[#ImeDRefOut]]
+CHECK: OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeMotionVectorsINTEL
{{.*}} %[[#ImeSRefOut]]
+CHECK: OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeMotionVectorsINTEL
{{.*}} %[[#ImeDRefOut]]
+CHECK: OpSubgroupAvcImeGetStreamoutSingleReferenceMajorShapeReferenceIdsINTEL
{{.*}} %[[#ImeSRefOut]]
+CHECK: OpSubgroupAvcImeGetStreamoutDualReferenceMajorShapeReferenceIdsINTEL
{{.*}} %[[#ImeDRefOut]]
+CHECK: OpSubgroupAvcImeSetDualReferenceINTEL %[[#ImePayloadTy]] {{.*}}
%[[#ImePayload]]
+CHECK: OpSubgroupAvcImeSetWeightedSadINTEL %[[#ImePayloadTy]] {{.*}}
%[[#ImePayload]]
+CHECK: OpSubgroupAvcImeSetEarlySearchTerminationThresholdINTEL
%[[#ImePayloadTy]] {{.*}} %[[#ImePayload]]
+CHECK: OpSubgroupAvcFmeInitializeINTEL %[[#RefPayloadTy]]
+CHECK: OpSubgroupAvcBmeInitializeINTEL %[[#RefPayloadTy]]
+
+CHECK: OpSubgroupAvcRefSetBidirectionalMixDisableINTEL
%[[#RefPayloadTy]]{{.*}}%[[#RefPayload]]
+
+CHECK: OpSubgroupAvcSicInitializeINTEL %[[#SicPayloadTy]]
+CHECK: OpSubgroupAvcSicConfigureIpeLumaINTEL %[[#SicPayloadTy]] {{.*}}
%[[#SicPayload]]
+CHECK: OpSubgroupAvcSicConfigureIpeLumaChromaINTEL %[[#SicPayloadTy]] {{.*}}
%[[#SicPayload]]
+CHECK: OpSubgroupAvcSicConfigureSkcINTEL %[[#SicPayloadTy]] {{.*}}
%[[#SicPayload]]
+CHECK: OpSubgroupAvcSicSetSkcForwardTransformEnableINTEL %[[#SicPayloadTy]]
{{.*}} %[[#SicPayload]]
+CHECK: OpSubgroupAvcSicSetBlockBasedRawSkipSadINTEL %[[#SicPayloadTy]] {{.*}}
%[[#SicPayload]]
+CHECK: OpSubgroupAvcSicSetIntraLumaShapePenaltyINTEL %[[#SicPayloadTy]] {{.*}}
%[[#SicPayload]]
+CHECK: OpSubgroupAvcSicSetIntraLumaModeCostFunctionINTEL %[[#SicPayloadTy]]
{{.*}} %[[#SicPayload]]
+CHECK: OpSubgroupAvcSicSetIntraChromaModeCostFunctionINTEL %[[#SicPayloadTy]]
{{.*}} %[[#SicPayload]]
+CHECK: OpSubgroupAvcSicGetBestIpeLumaDistortionINTEL {{.*}} %[[#SicResult]]
+CHECK: OpSubgroupAvcSicGetMotionVectorMaskINTEL
+
+CHECK: OpSubgroupAvcMceSetSourceInterlacedFieldPolarityINTEL
%[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+CHECK: OpSubgroupAvcMceSetSingleReferenceInterlacedFieldPolarityINTEL
%[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+CHECK: OpSubgroupAvcMceSetDualReferenceInterlacedFieldPolaritiesINTEL
%[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+CHECK: OpSubgroupAvcMceSetInterBaseMultiReferencePenaltyINTEL
%[[#McePayloadTy]] {{.*}} %[[#McePayload]]
+CHECK: OpSubgroupAvcMceSetInterShapePenaltyINTEL %[[#McePayloadTy]] {{.*}}
%[[#McePayload]]
+CHECK: OpSubgroupAvcMceSetInterDirectionPenaltyINTEL %[[#McePayloadTy]] {{.*}}
%[[#McePayload]]
+CHECK: OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL %[[#McePayloadTy]]
{{.*}} %[[#McePayload]]
+CHECK: OpSubgroupAvcMceGetInterReferenceInterlacedFieldPolaritiesINTEL {{.*}}
%[[#MceResult]]
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_not_builtin.ll.ll
b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_not_builtin.ll.ll
new file mode 100644
index 0000000000000..857de8d597653
--- /dev/null
+++
b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_not_builtin.ll.ll
@@ -0,0 +1,12 @@
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_INTEL_device_side_avc_motion_estimation %s -o - | FileCheck %s
+; XFAIL: *
+
+; CHECK: OpName %[[#Name:]] "_Z31intel_sub_group_avc_mce_ime_boo"
+; CHECK: %[[#]] = OpFunctionCall %[[#]] %[[#Name]]
+
+define spir_func void @foo() {
+entry:
+ call spir_func void @_Z31intel_sub_group_avc_mce_ime_boo()
+ ret void
+}
+declare spir_func void @_Z31intel_sub_group_avc_mce_ime_boo()
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_types.ll
b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_types.ll
new file mode 100644
index 0000000000000..23ff84ed0e13e
--- /dev/null
+++
b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_types.ll
@@ -0,0 +1,48 @@
+; RUN:llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_INTEL_device_side_avc_motion_estimation %s -o - | FileCheck %s
+; XFAIL: *
+
+; CHECK: OpCapability Groups
+; CHECK: OpCapability SubgroupAvcMotionEstimationINTEL
+; CHECK: OpExtension "SPV_INTEL_device_side_avc_motion_estimation"
+
+; CHECK: OpTypeAvcMcePayloadINTEL
+; CHECK: %[[#IME_PAYLOAD:]] = OpTypeAvcImePayloadINTEL
+; CHECK: %[[#REF_PAYLOAD:]] = OpTypeAvcRefPayloadINTEL
+; CHECK: %[[#SIC_PAYLOAD:]] = OpTypeAvcSicPayloadINTEL
+; CHECK: OpTypeAvcMceResultINTEL
+; CHECK: %[[#IME_RESULT:]] = OpTypeAvcImeResultINTEL
+; CHECK: %[[#REF_RESULT:]] = OpTypeAvcRefResultINTEL
+; CHECK: %[[#SIC_RESULT:]] = OpTypeAvcSicResultINTEL
+; CHECK: %[[#SSTREAMOUT:]] = OpTypeAvcImeResultSingleReferenceStreamoutINTEL
+; CHECK: %[[#DSTREAMOUT:]] = OpTypeAvcImeResultDualReferenceStreamoutINTEL
+; CHECK: %[[#SSTREAMIN:]] = OpTypeAvcImeSingleReferenceStreaminINTEL
+; CHECK: %[[#DSTREAMIN:]] = OpTypeAvcImeDualReferenceStreaminINTEL
+
+define spir_func void @foo() {
+entry:
+ %payload_mce = alloca target("spirv.AvcMcePayloadINTEL"), align 4
+ %payload_ime = alloca target("spirv.AvcImePayloadINTEL"), align 4
+ %payload_ref = alloca target("spirv.AvcRefPayloadINTEL"), align 4
+ %payload_sic = alloca target("spirv.AvcSicPayloadINTEL"), align 4
+ %result_mce = alloca target("spirv.AvcMceResultINTEL"), align 4
+ %result_ime = alloca target("spirv.AvcImeResultINTEL"), align 4
+ %result_ref = alloca target("spirv.AvcRefResultINTEL"), align 4
+ %result_sic = alloca target("spirv.AvcSicResultINTEL"), align 4
+ %sstreamout = alloca
target("spirv.AvcImeResultSingleReferenceStreamoutINTEL"), align 4
+ %dstreamout = alloca
target("spirv.AvcImeResultDualReferenceStreamoutINTEL"), align 4
+ %sstreamin = alloca target("spirv.AvcImeSingleReferenceStreaminINTEL"),
align 4
+ %dstreamin = alloca target("spirv.AvcImeDualReferenceStreaminINTEL"), align 4
+ store target("spirv.AvcMcePayloadINTEL") zeroinitializer, ptr %payload_mce,
align 4
+ store target("spirv.AvcImePayloadINTEL") zeroinitializer, ptr %payload_ime,
align 4
+ store target("spirv.AvcRefPayloadINTEL") zeroinitializer, ptr %payload_ref,
align 4
+ store target("spirv.AvcSicPayloadINTEL") zeroinitializer, ptr %payload_sic,
align 4
+ store target("spirv.AvcMceResultINTEL") zeroinitializer, ptr %result_mce,
align 4
+ store target("spirv.AvcImeResultINTEL") zeroinitializer, ptr %result_ime,
align 4
+ store target("spirv.AvcRefResultINTEL") zeroinitializer, ptr %result_ref,
align 4
+ store target("spirv.AvcSicResultINTEL") zeroinitializer, ptr %result_sic,
align 4
+ store target("spirv.AvcImeResultSingleReferenceStreamoutINTEL")
zeroinitializer, ptr %sstreamout, align 4
+ store target("spirv.AvcImeResultDualReferenceStreamoutINTEL")
zeroinitializer, ptr %dstreamout, align 4
+ store target("spirv.AvcImeSingleReferenceStreaminINTEL") zeroinitializer,
ptr %sstreamin, align 4
+ store target("spirv.AvcImeDualReferenceStreaminINTEL") zeroinitializer, ptr
%dstreamin, align 4
+ ret void
+}
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_wrappers.ll.ll
b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_wrappers.ll.ll
new file mode 100644
index 0000000000000..2ee4d4731c5e4
--- /dev/null
+++
b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_wrappers.ll.ll
@@ -0,0 +1,86 @@
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_INTEL_device_side_avc_motion_estimation %s -o - | FileCheck %s
+; XFAIL: *
+
+; CHECK: OpCapability Groups
+; CHECK: OpCapability SubgroupAvcMotionEstimationINTEL
+; CHECK: OpExtension "SPV_INTEL_device_side_avc_motion_estimation"
+
+; CHECK-DAG: %[[#ImePayloadTy:]] = OpTypeAvcImePayloadINTEL
+; CHECK-DAG: %[[#ImeResultTy:]] = OpTypeAvcImeResultINTEL
+; CHECK-DAG: %[[#RefPayloadTy:]] = OpTypeAvcRefPayloadINTEL
+; CHECK-DAG: %[[#RefResultTy:]] = OpTypeAvcRefResultINTEL
+; CHECK-DAG: %[[#SicPayloadTy:]] = OpTypeAvcSicPayloadINTEL
+; CHECK-DAG: %[[#SicResultTy:]] = OpTypeAvcSicResultINTEL
+; CHECK-DAG: %[[#McePayloadTy:]] = OpTypeAvcMcePayloadINTEL
+; CHECK-DAG: %[[#MceResultTy:]] = OpTypeAvcMceResultINTEL
+
+define spir_func void @test() #0 {
+entry:
+ %ime_payload = alloca target("spirv.AvcImePayloadINTEL"), align 8
+ %ime_result = alloca target("spirv.AvcImeResultINTEL"), align 8
+ %ref_payload = alloca target("spirv.AvcRefPayloadINTEL"), align 8
+ %ref_result = alloca target("spirv.AvcRefResultINTEL"), align 8
+ %sic_payload = alloca target("spirv.AvcSicPayloadINTEL"), align 8
+ %sic_result = alloca target("spirv.AvcSicResultINTEL"), align 8
+
+; CHECK: %[[#ImePayload:]] = OpLoad %[[#ImePayloadTy]]
+; CHECK: %[[#ImeResult:]] = OpLoad %[[#ImeResultTy]]
+; CHECK: %[[#RefPayload:]] = OpLoad %[[#RefPayloadTy]]
+; CHECK: %[[#RefResult:]] = OpLoad %[[#RefResultTy]]
+; CHECK: %[[#SicPayload:]] = OpLoad %[[#SicPayloadTy]]
+; CHECK: %[[#SicResult:]] = OpLoad %[[#SicResultTy]]
+
+ %0 = load target("spirv.AvcImePayloadINTEL"),
target("spirv.AvcImePayloadINTEL")* %ime_payload, align 8
+ %1 = load target("spirv.AvcImeResultINTEL"),
target("spirv.AvcImeResultINTEL")* %ime_result, align 8
+ %2 = load target("spirv.AvcRefPayloadINTEL"),
target("spirv.AvcRefPayloadINTEL")* %ref_payload, align 8
+ %3 = load target("spirv.AvcRefResultINTEL"),
target("spirv.AvcRefResultINTEL")* %ref_result, align 8
+ %4 = load target("spirv.AvcSicPayloadINTEL"),
target("spirv.AvcSicPayloadINTEL")* %sic_payload, align 8
+ %5 = load target("spirv.AvcSicResultINTEL"),
target("spirv.AvcSicResultINTEL")* %sic_result, align 8
+
+; CHECK: %[[#ImeMcePayloadConv:]] =
OpSubgroupAvcImeConvertToMcePayloadINTEL
+; CHECK-SAME: %[[#McePayloadTy]] %[[#ImePayload]]
+; CHECK: %[[#McePayloadRet0:]] =
OpSubgroupAvcMceSetInterBaseMultiReferencePenaltyINTEL
+; CHECK-SAME: %[[#McePayloadTy]] {{.*}} %[[#ImeMcePayloadConv]]
+; CHECK: OpSubgroupAvcMceConvertToImePayloadINTEL
+; CHECK-SAME: %[[#ImePayloadTy]] %[[#McePayloadRet0]]
+ %call0 = call spir_func target("spirv.AvcImePayloadINTEL")
@_Z62intel_sub_group_avc_ime_set_inter_base_multi_reference_penaltyh37ocl_intel_sub_group_avc_ime_payload_t(i8
zeroext 0, target("spirv.AvcImePayloadINTEL") %0) #2
+
+; CHECK: %[[#ImeMceResultConv:]] = OpSubgroupAvcImeConvertToMceResultINTEL
+; CHECK-SAME: %[[#MceResultTy]] %[[#ImeResult]]
+; CHECK: OpSubgroupAvcMceGetMotionVectorsINTEL {{.*}}
%[[#ImeMceResultConv]]
+ %call1 = call spir_func i64
@_Z42intel_sub_group_avc_ime_get_motion_vectors36ocl_intel_sub_group_avc_ime_result_t(target("spirv.AvcImeResultINTEL")
%1) #2
+
+; CHECK: %[[#RefMcePayloadConv:]] =
OpSubgroupAvcRefConvertToMcePayloadINTEL
+; CHECK-SAME: %[[#McePayloadTy]] %[[#RefPayload]]
+; CHECK: %[[#McePayloadRet1:]] = OpSubgroupAvcMceSetInterShapePenaltyINTEL
+; CHECK-SAME: %[[#McePayloadTy]] {{.*}} %[[#RefMcePayloadConv]]
+; CHECK: OpSubgroupAvcMceConvertToRefPayloadINTEL
+; CHECK-SAME: %[[#RefPayloadTy]] %[[#McePayloadRet1]]
+ %call2 = call spir_func target("spirv.AvcRefPayloadINTEL")
@_Z47intel_sub_group_avc_ref_set_inter_shape_penaltym37ocl_intel_sub_group_avc_ref_payload_t(i64
0, target("spirv.AvcRefPayloadINTEL") %2) #2
+
+; CHECK: %[[#RefMceResultConv:]] = OpSubgroupAvcRefConvertToMceResultINTEL
+; CHECK-SAME: %[[#MceResultTy]] %[[#RefResult]]
+; CHECK: OpSubgroupAvcMceGetInterDistortionsINTEL {{.*}}
%[[#RefMceResultConv]]
+ %call3 = call spir_func zeroext i16
@_Z45intel_sub_group_avc_ref_get_inter_distortions36ocl_intel_sub_group_avc_ref_result_t(target("spirv.AvcRefResultINTEL")
%3) #2
+
+; CHECK: %[[#SicMcePayloadConv:]] =
OpSubgroupAvcSicConvertToMcePayloadINTEL
+; CHECK-SAME: %[[#McePayloadTy]] %[[#SicPayload]]
+; CHECK: %[[#McePayloadRet2:]] =
OpSubgroupAvcMceSetMotionVectorCostFunctionINTEL
+; CHECK-SAME: %[[#McePayloadTy]] {{.*}} %[[#SicMcePayloadConv]]
+; CHECK: OpSubgroupAvcMceConvertToSicPayloadINTEL
+; CHECK-SAME: %[[#SicPayloadTy]] %[[#McePayloadRet2]]
+ %call4 = call spir_func target("spirv.AvcSicPayloadINTEL")
@_Z55intel_sub_group_avc_sic_set_motion_vector_cost_functionmDv2_jh37ocl_intel_sub_group_avc_sic_payload_t(i64
0, <2 x i32> zeroinitializer, i8 zeroext 0, target("spirv.AvcSicPayloadINTEL")
%4) #2
+
+; CHECK: %[[#SicMceResultConv:]] = OpSubgroupAvcSicConvertToMceResultINTEL
+; CHECK-SAME: %[[#MceResultTy]] %[[#SicResult]]
+; CHECK: OpSubgroupAvcMceGetInterDistortionsINTEL {{.*}}
%[[#SicMceResultConv]]
+ %call5 = call spir_func zeroext i16
@_Z45intel_sub_group_avc_sic_get_inter_distortions36ocl_intel_sub_group_avc_sic_result_t(target("spirv.AvcSicResultINTEL")
%5) #2
+ ret void
+}
+
+declare spir_func target("spirv.AvcImePayloadINTEL")
@_Z62intel_sub_group_avc_ime_set_inter_base_multi_reference_penaltyh37ocl_intel_sub_group_avc_ime_payload_t(i8
zeroext, target("spirv.AvcImePayloadINTEL")) #1
+declare spir_func i64
@_Z42intel_sub_group_avc_ime_get_motion_vectors36ocl_intel_sub_group_avc_ime_result_t(target("spirv.AvcImeResultINTEL"))
#1
+declare spir_func target("spirv.AvcRefPayloadINTEL")
@_Z47intel_sub_group_avc_ref_set_inter_shape_penaltym37ocl_intel_sub_group_avc_ref_payload_t(i64,
target("spirv.AvcRefPayloadINTEL")) #1
+declare spir_func zeroext i16
@_Z45intel_sub_group_avc_ref_get_inter_distortions36ocl_intel_sub_group_avc_ref_result_t(target("spirv.AvcRefResultINTEL"))
#1
+declare spir_func target("spirv.AvcSicPayloadINTEL")
@_Z55intel_sub_group_avc_sic_set_motion_vector_cost_functionmDv2_jh37ocl_intel_sub_group_avc_sic_payload_t(i64,
<2 x i32>, i8 zeroext, target("spirv.AvcSicPayloadINTEL")) #1
+declare spir_func zeroext i16
@_Z45intel_sub_group_avc_sic_get_inter_distortions36ocl_intel_sub_group_avc_sic_result_t(target("spirv.AvcSicResultINTEL"))
#1
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fast_math_mode/fp_contract_reassoc_fast_mode.ll
b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fast_math_mode/fp_contract_reassoc_fast_mode.ll
new file mode 100644
index 0000000000000..b44f8281e4564
--- /dev/null
+++
b/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_fast_math_mode/fp_contract_reassoc_fast_mode.ll
@@ -0,0 +1,35 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o -
| FileCheck %s --check-prefix=CHECK-EXT-OFF
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown
--spirv-ext=+SPV_INTEL_fp_fast_math_mode %s -o - | FileCheck %s
--check-prefix=CHECK-EXT-ON
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_INTEL_fp_fast_math_mode %s -o - -filetype=obj | spirv-val %}
+; XFAIL: *
+
+; CHECK-EXT-ON: OpCapability FPFastMathModeINTEL
+; CHECK-EXT-ON: SPV_INTEL_fp_fast_math_mode
+; CHECK-EXT-ON: OpName %[[#mul:]] "mul"
+; CHECK-EXT-ON: OpName %[[#sub:]] "sub"
+; CHECK-EXT-ON: OpDecorate %[[#mu:]] FPFastMathMode AllowContract
+; CHECK-EXT-ON: OpDecorate %[[#su:]] FPFastMathMode AllowReassoc
+
+; CHECK-EXT-OFF-NOT: OpCapability FPFastMathModeINTEL
+; CHECK-EXT-OFF-NOT: SPV_INTEL_fp_fast_math_mode
+; CHECK-EXT-OFF: OpName %[[#mul:]] "mul"
+; CHECK-EXT-OFF: OpName %[[#sub:]] "sub"
+; CHECK-EXT-OFF-NOT: 4 Decorate %[[#mul]] FPFastMathMode AllowContract
+; CHECK-EXT-OFF-NOT: 4 Decorate %[[#sub]] FPFastMathMode AllowReassoc
+
+define spir_kernel void @test(float %a, float %b) {
+entry:
+ %a.addr = alloca float, align 4
+ %b.addr = alloca float, align 4
+ store float %a, ptr %a.addr, align 4
+ store float %b, ptr %b.addr, align 4
+ %0 = load float, ptr %a.addr, align 4
+ %1 = load float, ptr %a.addr, align 4
+ %mul = fmul contract float %0, %1
+ store float %mul, ptr %b.addr, align 4
+ %2 = load float, ptr %b.addr, align 4
+ %3 = load float, ptr %b.addr, align 4
+ %sub = fsub reassoc float %2, %3
+ store float %sub, ptr %b.addr, align 4
+ ret void
+}
diff --git a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16.ll
b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16.ll
new file mode 100644
index 0000000000000..f9230cebac704
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16.ll
@@ -0,0 +1,20 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown
--spirv-ext=+SPV_KHR_bfloat16 %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_KHR_bfloat16 %s -o - -filetype=obj | spirv-val %}
+; XFAIL: *
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o -
| FileCheck %s --check-prefix=CHECK-ERROR
+
+; CHECK-ERROR: BFloat16TypeKHR requires the following SPIR-V extension:
SPV_KHR_subgroup_rotate
+
+; CHECK-DAG: OpCapability BFloat16TypeKHR
+; CHECK-DAG: OpExtension "SPV_KHR_bfloat16"
+; CHECK: %[[#BFLOAT:]] = OpTypeFloat 16 0
+; CHECK: %[[#]] = OpTypeVector %[[#BFLOAT]] 2
+
+define spir_kernel void @test() {
+entry:
+ %addr1 = alloca bfloat
+ %addr2 = alloca <2 x bfloat>
+ %data1 = load bfloat, ptr %addr1
+ %data2 = load <2 x bfloat>, ptr %addr2
+ ret void
+}
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16_dot.ll
b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16_dot.ll
new file mode 100644
index 0000000000000..337eda538c196
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/bfloat16_dot.ll
@@ -0,0 +1,22 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown
--spirv-ext=+SPV_KHR_bfloat16 %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_KHR_bfloat16 %s -o - -filetype=obj | spirv-val %}
+; XFAIL: *
+
+; CHECK-SPIRV-DAG: OpCapability BFloat16TypeKHR
+; CHECK-SPIRV-DAG: OpCapability BFloat16DotProductKHR
+; CHECK-SPIRV-DAG: OpExtension "SPV_KHR_bfloat16"
+; CHECK-SPIRV: %[[#BFLOAT:]] = OpTypeFloat 16 0
+; CHECK-SPIRV: %[[#]] = OpTypeVector %[[#BFLOAT]] 2
+; CHECK-SPIRV: OpDot
+
+declare spir_func bfloat @_Z3dotDv2_u6__bf16Dv2_S_(<2 x bfloat>, <2 x bfloat>)
+
+define spir_kernel void @test() {
+entry:
+ %addrA = alloca <2 x bfloat>
+ %addrB = alloca <2 x bfloat>
+ %dataA = load <2 x bfloat>, ptr %addrA
+ %dataB = load <2 x bfloat>, ptr %addrB
+ %call = call spir_func bfloat @_Z3dotDv2_u6__bf16Dv2_S_(<2 x bfloat> %dataA,
<2 x bfloat> %dataB)
+ ret void
+}
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/cooperative_matrix_bfloat16.ll
b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/cooperative_matrix_bfloat16.ll
new file mode 100644
index 0000000000000..6dd8fb7f0e83e
--- /dev/null
+++
b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_bfloat16/cooperative_matrix_bfloat16.ll
@@ -0,0 +1,25 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown
--spirv-ext=+SPV_KHR_cooperative_matrix,+SPV_KHR_bfloat16 %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_KHR_cooperative_matrix,+SPV_KHR_bfloat16 %s -o - -filetype=obj
| spirv-val %}
+; XFAIL: *
+
+; CHECK-SPIRV-DAG: OpCapability CooperativeMatrixKHR
+; CHECK-SPIRV-DAG: OpCapability BFloat16TypeKHR
+; CHECK-SPIRV-DAG: OpCapability BFloat16CooperativeMatrixKHR
+; CHECK-SPIRV-DAG: OpExtension "SPV_KHR_cooperative_matrix"
+; CHECK-SPIRV-DAG: OpExtension "SPV_KHR_bfloat16"
+
+; CHECK-SPIRV-DAG: %[[#BFloatTy:]] = OpTypeFloat 16 0
+; CHECK-SPIRV-DAG: %[[#Int32Ty:]]= OpTypeInt 32 0
+; CHECK-SPIRV-DAG: %[[#Const12:]] = OpConstant %[[#Int32Ty]] 12
+; CHECK-SPIRV-DAG: %[[#Const3:]] = OpConstant %[[#Int32Ty]] 3
+; CHECK-SPIRV-DAG: %[[#Const2:]] = OpConstant %[[#Int32Ty]] 2
+; CHECK-SPIRV-DAG: %[[#MatTy:]] = OpTypeCooperativeMatrixKHR %[[#BFloatTy]]
%[[#Const3]] %[[#Const12]] %[[#Const12]] %[[#Const2]]
+; CHECK-SPIRV-DAG: %[[#]] = OpConstant %[[#BFloatTy]] 16256
+; CHECK-SPIRV: %[[#]] = OpCompositeConstruct %[[#MatTy]]
+
+declare spir_func target("spirv.CooperativeMatrixKHR", bfloat, 3, 12, 12, 2)
@_Z26__spirv_CompositeConstructu6__bf16(bfloat)
+
+define spir_kernel void @test() {
+ %mat = call spir_func target("spirv.CooperativeMatrixKHR", bfloat, 3, 12,
12, 2) @_Z26__spirv_CompositeConstructu6__bf16(bfloat 1.0)
+ ret void
+}
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/globals.ll
b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/globals.ll
new file mode 100644
index 0000000000000..5d2e44c8b760e
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/globals.ll
@@ -0,0 +1,48 @@
+; This test validated untyped access chain and its use in SpecConstantOp.
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown
--spirv-ext=+SPV_KHR_untyped_pointers %s -o - | FileCheck %s
+; TODO: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_KHR_untyped_pointers %s -o - -filetype=obj | spirv-val %}
+
+; TODO: enable back once spirv-tools are updated and allow untyped access
chain as OpSpecConstantOp operand.
+; XFAIL: *
+
+; CHECK-DAG: %[[#I16:]] = OpTypeInt 16 0
+; CHECK-DAG: %[[#I32:]] = OpTypeInt 32 0
+; CHECK-DAG: %[[#I64:]] = OpTypeInt 64 0
+; CHECK-DAG: %[[#CONST0:]] = OpConstant %[[#I16]] 0
+; CHECK-DAG: %[[#CONST2:]] = OpConstant %[[#I32]] 2
+; CHECK-DAG: %[[#CONST3:]] = OpConstant %[[#I32]] 3
+; CHECK-DAG: %[[#CONST4:]] = OpConstant %[[#I32]] 4
+; CHECK-DAG: %[[#CONST0_I64:]] = OpConstant %[[#I64]] 0
+; CHECK-DAG: %[[#CONST1_I64:]] = OpConstant %[[#I64]] 1
+; CHECK-DAG: %[[#CONST2_I64:]] = OpConstant %[[#I64]] 2
+; CHECK-DAG: %[[#CONST3_I64:]] = OpConstant %[[#I64]] 3
+
+; CHECK-DAG: %[[#PTRTY:]] = OpTypeUntypedPointerKHR 5
+; CHECK-DAG: %[[#LOCALPTRTY:]] = OpTypeUntypedPointerKHR 4
+; CHECK-DAG: %[[#ARRAYTY:]] = OpTypeArray %[[#PTRTY]] %[[#CONST2]]
+; CHECK-DAG: %[[#ARRAYPTRTY:]] = OpTypePointer 5 %[[#ARRAYTY]]
+; CHECK-DAG: %[[#ARRAY1TY:]] = OpTypeArray %[[#I32]] %[[#CONST4]]
+; CHECK-DAG: %[[#ARRAY2TY:]] = OpTypeArray %[[#ARRAY1TY]] %[[#CONST3]]
+; CHECK-DAG: %[[#ARRAY3TY:]] = OpTypeArray %[[#ARRAY2TY]] %[[#CONST2]]
+; CHECK-DAG: %[[#ARRAY3PTRTY:]] = OpTypePointer 5 %[[#ARRAY3TY]]
+; CHECK: %[[#VARA:]] = OpUntypedVariableKHR %[[#PTRTY]] 5 %[[#I16]]
%[[#CONST0]]
+; CHECK: %[[#VARB:]] = OpUntypedVariableKHR %[[#PTRTY]] 5 %[[#I32]]
+; CHECK: %[[#VARC:]] = OpUntypedVariableKHR %[[#PTRTY]] 5 %[[#PTRTY]]
%[[#VARA]]
+; CHECK: %[[#VARD:]] = OpUntypedVariableKHR %[[#LOCALPTRTY]] 4 %[[#PTRTY]]
+; CHECK: %[[#VARE:]] = OpVariable %[[#ARRAYPTRTY]] 5
+; CHECK: %[[#VARF:]] = OpVariable %[[#ARRAY3PTRTY]] 5
+; CHECK: %[[#SPECCONST:]] = OpSpecConstantOp %[[#PTRTY]] 4424 %[[#ARRAY3TY]]
%[[#VARF]] %[[#CONST0_I64]] %[[#CONST1_I64]] %[[#CONST2_I64]] %[[#CONST3_I64]]
+; CHECK: %[[#VARG:]] = OpUntypedVariableKHR %[[#PTRTY]] 5 %[[#PTRTY]]
%[[#SPECCONST]]
+
+@a = addrspace(1) global i16 0
+@b = external addrspace(1) global i32
+@c = addrspace(1) global ptr addrspace(1) @a
+@d = external addrspace(3) global ptr addrspace(1)
+@e = addrspace(1) global [2 x ptr addrspace(1)] [ptr addrspace(1) @a, ptr
addrspace(1) @b]
+@f = addrspace(1) global [2 x [3 x [4 x i32]]] [[3 x [4 x i32]] [[4 x i32]
[i32 1, i32 2, i32 3, i32 4], [4 x i32] [i32 1, i32 2, i32 3, i32 4], [4 x i32]
[i32 1, i32 2, i32 3, i32 4]], [3 x [4 x i32]] [[4 x i32] [i32 1, i32 2, i32 3,
i32 4], [4 x i32] [i32 1, i32 2, i32 3, i32 4], [4 x i32] [i32 1, i32 2, i32 3,
i32 4]]]
+@g = addrspace(1) global ptr addrspace(1) getelementptr inbounds ([2 x [3 x [4
x i32]]], ptr addrspace(1) @f, i64 0, i64 1, i64 2, i64 3)
+
+define spir_func void @foo() {
+entry:
+ ret void
+}
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/infinite-phi.ll
b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/infinite-phi.ll
new file mode 100644
index 0000000000000..0ee2f2a5277a2
--- /dev/null
+++
b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/infinite-phi.ll
@@ -0,0 +1,35 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown
--spirv-ext=+SPV_KHR_untyped_pointers %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_KHR_untyped_pointers %s -o - -filetype=obj | spirv-val %}
+; XFAIL: *
+
+; CHECK-DAG: [[#I32:]] = OpTypeInt 32 0
+; CHECK-DAG: [[#VOID:]] = OpTypeVoid
+; CHECK-DAG: [[#FN_BAR_TY:]] = OpTypeFunction [[#I32]] [[#I32]]
+; CHECK-DAG: [[#FN_FOO_TY:]] = OpTypeFunction [[#VOID]] [[#I32]]
+
+; CHECK-DAG: [[#BAR:]] = OpFunction [[#I32]] None [[#FN_BAR_TY]]
+; CHECK-DAG: OpFunctionEnd
+
+; CHECK-DAG: [[#FOO:]] = OpFunction [[#VOID]] None [[#FN_FOO_TY]]
+; CHECK: [[#PARAM_X:]] = OpFunctionParameter [[#I32]]
+; CHECK: [[#CALL1:]] = OpFunctionCall [[#I32]] [[#BAR]] [[#PARAM_X]]
+; CHECK: OpReturn
+; CHECK: OpFunctionEnd
+
+define spir_kernel void @foo() {
+entry:
+ %iptr = alloca i32, align 4
+ %fptr = alloca float, align 4
+ br label %loop
+
+loop:
+ %ptr1 = phi ptr [%ptr2, %loop], [%iptr, %entry]
+ %ptr2 = phi ptr [%ptr1, %loop], [%fptr, %entry]
+ %cond = phi i32 [0, %entry], [%cond.next, %loop]
+ %cond.next = add i32 %cond, 1
+ %cmp = icmp slt i32 %cond.next, 150
+ br i1 %cmp, label %exit, label %loop
+
+exit:
+ ret void
+}
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/read_image.ll
b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/read_image.ll
new file mode 100644
index 0000000000000..e294269b1b35e
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/read_image.ll
@@ -0,0 +1,51 @@
+; Check that untyped pointers extension does not affect the translation of
images.
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown
--spirv-ext=+SPV_KHR_untyped_pointers %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_KHR_untyped_pointers %s -o - -filetype=obj | spirv-val %}
+; XFAIL: *
+
+; CHECK-DAG: [[#I32:]] = OpTypeInt 32 0
+; CHECK-DAG: [[#IMAGETY:]] = OpTypeImage [[#I32]] 2 0 0 0 0 0 0
+; CHECK-DAG: [[#IVEC:]] = OpTypeVector [[#I32]] [[#]]
+; CHECK-DAG: [[#F32:]] = OpTypeFloat 32
+; CHECK-DAG: [[#FVEC:]] = OpTypeVector [[#F32]] [[#]]
+
+; CHECK: [[#IMAGE0:]] = OpLoad [[#IMAGETY]] [[#]]
+; CHECK: [[#COORD0:]] = OpLoad [[#IVEC]] [[#]]
+; CHECK: [[#]] = OpImageRead [[#IVEC]] [[#IMAGE0]] [[#COORD0]] 8192
+
+; CHECK: [[#IMAGE1:]] = OpLoad [[#IMAGETY]] [[#]]
+; CHECK: [[#COORD1:]] = OpLoad [[#IVEC]] [[#]]
+; CHECK: [[#]] = OpImageRead [[#FVEC]] [[#IMAGE1]] [[#COORD1]]
+
+define dso_local spir_kernel void @kernelA(target("spirv.Image", void, 2, 0,
0, 0, 0, 0, 0) %input) {
+entry:
+ %input.addr = alloca target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 0), align
8
+ %c = alloca <4 x i32>, align 16
+ %.compoundliteral = alloca <4 x i32>, align 16
+ store target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 0) %input, ptr
%input.addr, align 8
+ %0 = load target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 0), ptr %input.addr,
align 8
+ store <4 x i32> zeroinitializer, ptr %.compoundliteral, align 16
+ %1 = load <4 x i32>, ptr %.compoundliteral, align 16
+ %call = call spir_func <4 x i32>
@_Z12read_imageui14ocl_image3d_roDv4_i(target("spirv.Image", void, 2, 0, 0, 0,
0, 0, 0) %0, <4 x i32> noundef %1)
+ store <4 x i32> %call, ptr %c, align 16
+ ret void
+}
+
+declare spir_func <4 x i32>
@_Z12read_imageui14ocl_image3d_roDv4_i(target("spirv.Image", void, 2, 0, 0, 0,
0, 0, 0), <4 x i32> noundef)
+
+define dso_local spir_kernel void @kernelB(target("spirv.Image", void, 2, 0,
0, 0, 0, 0, 0) %input) {
+entry:
+ %input.addr = alloca target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 0), align
8
+ %f = alloca <4 x float>, align 16
+ %.compoundliteral = alloca <4 x i32>, align 16
+ store target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 0) %input, ptr
%input.addr, align 8
+ %0 = load target("spirv.Image", void, 2, 0, 0, 0, 0, 0, 0), ptr %input.addr,
align 8
+ store <4 x i32> zeroinitializer, ptr %.compoundliteral, align 16
+ %1 = load <4 x i32>, ptr %.compoundliteral, align 16
+ %call = call spir_func <4 x float>
@_Z11read_imagef14ocl_image3d_roDv4_i(target("spirv.Image", void, 2, 0, 0, 0,
0, 0, 0) %0, <4 x i32> noundef %1)
+ store <4 x float> %call, ptr %f, align 16
+ ret void
+}
+
+declare spir_func <4 x float>
@_Z11read_imagef14ocl_image3d_roDv4_i(target("spirv.Image", void, 2, 0, 0, 0,
0, 0, 0), <4 x i32> noundef)
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/store.ll
b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/store.ll
new file mode 100644
index 0000000000000..0ffc8f6eed88b
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/store.ll
@@ -0,0 +1,47 @@
+; This test checks translation of function parameter which is untyped pointer.
+; Lately, when we do support untyped variables, this one could be used to check
+; "full" forward and reverse translation of opaque pointers.
+
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown
--spirv-ext=+SPV_KHR_untyped_pointers %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_KHR_untyped_pointers %s -o - -filetype=obj | spirv-val %}
+; XFAIL: *
+
+; CHECK: Capability [[#]] = OpCapability UntypedPointersKHR
+; CHECK: Extension [[#]] = OpExtension "SPV_KHR_untyped_pointers"
+
+; CHECK-DAG: [[#IntTy:]] = OpTypeInt 32 0
+; CHECK-DAG: [[#Constant0:]] = OpConstant [[#IntTy]] 0
+; CHECK-DAG: [[#Constant42:]] = OpConstant [[#IntTy]] 42
+; CHECK-DAG: [[#UntypedPtrTy:]] = OpTypeUntypedPointerKHR 5
+; CHECK-DAG: [[#UntypedPtrTyFunc:]] = OpTypeUntypedPointerKHR 7
+
+; CHECK: [[#FuncParam:]] = OpFunctionParameter [[#UntypedPtrTy]]
+; CHECK: [[#VarBId:]] = OpUntypedVariableKHR [[#UntypedPtrTyFunc]] 7
[[#UntypedPtrTy]]
+; CHECK: OpStore [[#VarBId]] [[#FuncParam]] 2 4
+; CHECK: [[#LoadId:]] = OpLoad [[#UntypedPtrTy]] [[#VarBId]] 2 4
+; CHECK: OpStore [[#LoadId]] [[#Constant0]] 2 4
+
+; CHECK: [[#FuncParam0:]] = OpFunctionParameter [[#UntypedPtrTy]]
+; CHECK: [[#FuncParam1:]] = OpFunctionParameter [[#UntypedPtrTy]]
+; CHECK: [[#VarCId:]] = OpUntypedVariableKHR [[#UntypedPtrTyFunc]] 7 [[#IntTy]]
+; CHECK: OpStore [[#VarCId]] [[#Constant42]] 2 4
+; CHECK: [[#LoadId:]] = OpLoad [[#IntTy]] [[#FuncParam1]] 2 4
+; CHECK: OpStore [[#FuncParam0]] [[#LoadId]] 2 4
+
+define spir_func void @foo(ptr addrspace(1) %a) {
+entry:
+ %b = alloca ptr addrspace(1), align 4
+ store ptr addrspace(1) %a, ptr %b, align 4
+ %0 = load ptr addrspace(1), ptr %b, align 4
+ store i32 0, ptr addrspace(1) %0, align 4
+ ret void
+}
+
+define dso_local void @boo(ptr addrspace(1) %0, ptr addrspace(1) %1) {
+entry:
+ %c = alloca i32, align 4
+ store i32 42, ptr %c, align 4
+ %2 = load i32, ptr addrspace(1) %1, align 4
+ store i32 %2, ptr addrspace(1) %0, align 4
+ ret void
+}
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/untyped_ptr_access_chain.ll
b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/untyped_ptr_access_chain.ll
new file mode 100644
index 0000000000000..d599cb08ae468
--- /dev/null
+++
b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/untyped_ptr_access_chain.ll
@@ -0,0 +1,26 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown
--spirv-ext=+SPV_KHR_untyped_pointers %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_KHR_untyped_pointers %s -o - -filetype=obj | spirv-val %}
+; XFAIL: *
+
+; CHECK-SPIRV: OpCapability UntypedPointersKHR
+; CHECK-SPIRV: OpExtension "SPV_KHR_untyped_pointers"
+
+; CHECK-SPIRV: OpTypeInt [[#IntTy:]] 32
+; CHECK-SPIRV: OpConstant [[#IntTy]] [[#Const0:]] 0
+; CHECK-SPIRV: OpConstant [[#IntTy]] [[#Const1:]] 1
+; CHECK-SPIRV: OpTypeUntypedPointerKHR [[#UntypedPtrTy:]] 7
+; CHECK-SPIRV: OpTypeStruct [[#StructTy:]] [[#IntTy]] [[#IntTy]]
+; CHECK-SPIRV: OpUntypedVariableKHR [[#UntypedPtrTy]] [[#StructVarId:]] 7
[[#StructTy]]
+; CHECK-SPIRV: OpUntypedInBoundsPtrAccessChainKHR [[#UntypedPtrTy]]
[[#PtrAccessId:]] [[#StructTy]] [[#StructVarId]] [[#Const0]] [[#Const1]]
+
+%struct.Example = type { i32, i32 }
+
+define spir_func void @test(i32 noundef %0) {
+ %2 = alloca i32, align 4
+ %3 = alloca %struct.Example, align 4
+ store i32 %0, ptr %2, align 4
+ %4 = load i32, ptr %2, align 4
+ %5 = getelementptr inbounds nuw %struct.Example, ptr %3, i32 0, i32 1
+ store i32 %4, ptr %5, align 4
+ ret void
+}
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/untyped_ptr_type.ll
b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/untyped_ptr_type.ll
new file mode 100644
index 0000000000000..3ec2e9807e59b
--- /dev/null
+++
b/llvm/test/CodeGen/SPIRV/extensions/SPV_KHR_untyped_pointers/untyped_ptr_type.ll
@@ -0,0 +1,24 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown
--spirv-ext=+SPV_KHR_untyped_pointers %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown
--spirv-ext=+SPV_KHR_untyped_pointers %s -o - -filetype=obj | spirv-val %}
+; XFAIL: *
+
+; CHECK: [[#cap_untyped_ptr:]] = OpCapability UntypedPointersKHR
+; CHECK: [[#ext_untyped_ptr:]] = OpExtension "SPV_KHR_untyped_pointers"
+; CHECK-DAG: [[#void_ty:]] = OpTypeVoid
+; CHECK-DAG: [[#untyped_ptr_ty:]] = OpTypeUntypedPointerKHR 7
+; CHECK-DAG: [[#func_ty:]] = OpTypeFunction [[#untyped_ptr_ty]]
[[#untyped_ptr_ty]]
+
+; CHECK: [[#process_func:]] = OpFunction [[#untyped_ptr_ty]] None [[#func_ty]]
+; CHECK: OpFunctionParameter [[#untyped_ptr_ty]]
+; CHECK: [[#main_func:]] = OpFunction [[#untyped_ptr_ty]] None [[#func_ty]]
+; CHECK: [[#param:]] = OpFunctionParameter [[#untyped_ptr_ty]]
+; CHECK: [[#call_res:]] = OpFunctionCall [[#untyped_ptr_ty]] [[#process_func]]
[[#param]]
+; CHECK: OpReturnValue [[#call_res]]
+
+declare ptr @processPointer(ptr)
+
+define ptr @example(ptr %arg) {
+entry:
+ %result = call ptr @processPointer(ptr %arg)
+ ret ptr %result
+}
>From 87146ff72b81ef0fb5b507de90be0be7f396c4e1 Mon Sep 17 00:00:00 2001
From: Aadesh PremKumar <aadesh.premku...@multicorewareinc.com>
Date: Thu, 14 Aug 2025 17:18:06 +0530
Subject: [PATCH 2/2] --Moved the test for the generic AVC motion estimation
from LLVM to Clang.
---
.../test/CodeGenOpenCL}/subgroup_avc_intel_generic.cl | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename
{llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation
=> clang/test/CodeGenOpenCL}/subgroup_avc_intel_generic.cl (100%)
diff --git
a/llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl
b/clang/test/CodeGenOpenCL/subgroup_avc_intel_generic.cl
similarity index 100%
rename from
llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_device_side_avc_motion_estimation/subgroup_avc_intel_generic.cl
rename to clang/test/CodeGenOpenCL/subgroup_avc_intel_generic.cl
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