https://github.com/topperc created
https://github.com/llvm/llvm-project/pull/153903
None
>From 30b3e701ff94691ff55aeb1297890eac71b59857 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.top...@sifive.com>
Date: Fri, 15 Aug 2025 16:31:29 -0700
Subject: [PATCH] [RISCV] Remove experimental from Smctr and Ssctr.
---
.../Driver/print-supported-extensions-riscv.c | 4 ++--
llvm/docs/ReleaseNotes.md | 1 +
llvm/lib/Target/RISCV/RISCVFeatures.td | 12 +++++-----
llvm/test/CodeGen/RISCV/attributes.ll | 8 +++----
llvm/test/CodeGen/RISCV/features-info.ll | 4 ++--
llvm/test/MC/RISCV/smctr-ssctr-valid.s | 24 +++++++++----------
.../TargetParser/RISCVISAInfoTest.cpp | 4 ++--
7 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c
b/clang/test/Driver/print-supported-extensions-riscv.c
index 2503f2473d64a..87bbd95877b25 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -128,6 +128,7 @@
// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter
Delegation Machine Level)
// CHECK-NEXT: smcntrpmf 1.0 'Smcntrpmf' (Cycle and
Instret Privilege Mode Filtering)
// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR
Access Machine Level)
+// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer
Records Machine Level)
// CHECK-NEXT: smdbltrp 1.0 'Smdbltrp' (Double Trap
Machine Level)
// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical
Memory Protection)
// CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level
Pointer Masking for M-mode)
@@ -140,6 +141,7 @@
// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow
and Mode-Based Filtering)
// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support
writeable scounteren enable bit for any hpmcounter that is not read-only zero)
// CHECK-NEXT: sscsrind 1.0 'Sscsrind' (Indirect CSR
Access Supervisor Level)
+// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer
Records Supervisor Level)
// CHECK-NEXT: ssdbltrp 1.0 'Ssdbltrp' (Double Trap
Supervisor Level)
// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level
Pointer Masking for next lower privilege mode)
// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates
Supervisor-mode Pointer Masking)
@@ -214,8 +216,6 @@
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless
Multiplication with 32-bits elements)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM
instructions for Cryptography)
// CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad
widening 4D Dot Product)
-// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer
Records Machine Level)
-// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer
Records Supervisor Level)
// CHECK-NEXT: svukte 0.3 'Svukte'
(Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
// CHECK-NEXT: xqccmp 0.3 'Xqccmp' (Qualcomm 16-bit
Push/Pop and Double Moves)
// CHECK-NEXT: xqcia 0.7 'Xqcia' (Qualcomm uC
Arithmetic Extension)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index ef7586a6bab7c..3b90c964ac53d 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -118,6 +118,7 @@ Changes to the RISC-V Backend
* `llvm-objdump` now has basic support for switching between disassembling code
and data using mapping symbols such as `$x` and `$d`. Switching architectures
using `$x` with an architecture string suffix is not yet supported.
+* Ssctr and Smctr extensions are no longer experimental.
Changes to the WebAssembly Backend
----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index a7329d201f880..ac0234dd9a5f5 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1055,13 +1055,13 @@ def FeatureStdExtSupm
"Indicates User-mode Pointer Masking">;
def FeatureStdExtSmctr
- : RISCVExperimentalExtension<1, 0,
- "Control Transfer Records Machine Level",
- [FeatureStdExtSscsrind]>;
+ : RISCVExtension<1, 0,
+ "Control Transfer Records Machine Level",
+ [FeatureStdExtSscsrind]>;
def FeatureStdExtSsctr
- : RISCVExperimentalExtension<1, 0,
- "Control Transfer Records Supervisor Level",
- [FeatureStdExtSscsrind]>;
+ : RISCVExtension<1, 0,
+ "Control Transfer Records Supervisor Level",
+ [FeatureStdExtSscsrind]>;
def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">,
AssemblerPredicate<(any_of FeatureStdExtSmctr,
FeatureStdExtSsctr),
"'Smctr' (Control Transfer Records Machine
Level) or "
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index a28b818b3db11..940e018ebdc9a 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -173,8 +173,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+smmpm %s -o - | FileCheck
--check-prefix=RV32SMMPM %s
; RUN: llc -mtriple=riscv32 -mattr=+sspm %s -o - | FileCheck
--check-prefix=RV32SSPM %s
; RUN: llc -mtriple=riscv32 -mattr=+supm %s -o - | FileCheck
--check-prefix=RV32SUPM %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-smctr %s -o - | FileCheck
--check-prefix=RV32SMCTR %s
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssctr %s -o - | FileCheck
--check-prefix=RV32SSCTR %s
+; RUN: llc -mtriple=riscv32 -mattr=+smctr %s -o - | FileCheck
--check-prefix=RV32SMCTR %s
+; RUN: llc -mtriple=riscv32 -mattr=+ssctr %s -o - | FileCheck
--check-prefix=RV32SSCTR %s
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck
--check-prefixes=CHECK,RV64M %s
@@ -336,8 +336,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+smmpm %s -o - | FileCheck
--check-prefix=RV64SMMPM %s
; RUN: llc -mtriple=riscv64 -mattr=+sspm %s -o - | FileCheck
--check-prefix=RV64SSPM %s
; RUN: llc -mtriple=riscv64 -mattr=+supm %s -o - | FileCheck
--check-prefix=RV64SUPM %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck
--check-prefix=RV64SMCTR %s
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck
--check-prefix=RV64SSCTR %s
+; RUN: llc -mtriple=riscv64 -mattr=+smctr %s -o - | FileCheck
--check-prefix=RV64SMCTR %s
+; RUN: llc -mtriple=riscv64 -mattr=+ssctr %s -o - | FileCheck
--check-prefix=RV64SSCTR %s
; RUN: llc -mtriple=riscv64 -mattr=+sdext %s -o - | FileCheck
--check-prefix=RV64SDEXT %s
; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck
--check-prefix=RV64SDTRIG %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck
--check-prefix=RV64XQCCMP %s
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll
b/llvm/test/CodeGen/RISCV/features-info.ll
index fb539211fcc31..60b94adcc4c79 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -27,8 +27,6 @@
; CHECK-NEXT: experimental - Experimental intrinsics.
; CHECK-NEXT: experimental-p - 'P' ('Base P' (Packed
SIMD)).
; CHECK-NEXT: experimental-rvm23u32 - RISC-V
experimental-rvm23u32 profile.
-; CHECK-NEXT: experimental-smctr - 'Smctr' (Control Transfer
Records Machine Level).
-; CHECK-NEXT: experimental-ssctr - 'Ssctr' (Control Transfer
Records Supervisor Level).
; CHECK-NEXT: experimental-svukte - 'Svukte'
(Address-Independent Latency of User-Mode Faults to Supervisor Addresses).
; CHECK-NEXT: experimental-xqccmp - 'Xqccmp' (Qualcomm 16-bit
Push/Pop and Double Moves).
; CHECK-NEXT: experimental-xqcia - 'Xqcia' (Qualcomm uC
Arithmetic Extension).
@@ -145,6 +143,7 @@
; CHECK-NEXT: smcdeleg - 'Smcdeleg' (Counter
Delegation Machine Level).
; CHECK-NEXT: smcntrpmf - 'Smcntrpmf' (Cycle and
Instret Privilege Mode Filtering).
; CHECK-NEXT: smcsrind - 'Smcsrind' (Indirect CSR
Access Machine Level).
+; CHECK-NEXT: smctr - 'Smctr' (Control Transfer
Records Machine Level).
; CHECK-NEXT: smdbltrp - 'Smdbltrp' (Double Trap
Machine Level).
; CHECK-NEXT: smepmp - 'Smepmp' (Enhanced Physical
Memory Protection).
; CHECK-NEXT: smmpm - 'Smmpm' (Machine-level
Pointer Masking for M-mode).
@@ -157,6 +156,7 @@
; CHECK-NEXT: sscofpmf - 'Sscofpmf' (Count Overflow
and Mode-Based Filtering).
; CHECK-NEXT: sscounterenw - 'Sscounterenw' (Support
writeable scounteren enable bit for any hpmcounter that is not read-only zero).
; CHECK-NEXT: sscsrind - 'Sscsrind' (Indirect CSR
Access Supervisor Level).
+; CHECK-NEXT: ssctr - 'Ssctr' (Control Transfer
Records Supervisor Level).
; CHECK-NEXT: ssdbltrp - 'Ssdbltrp' (Double Trap
Supervisor Level).
; CHECK-NEXT: ssnpm - 'Ssnpm' (Supervisor-level
Pointer Masking for next lower privilege mode).
; CHECK-NEXT: sspm - 'Sspm' (Indicates
Supervisor-mode Pointer Masking).
diff --git a/llvm/test/MC/RISCV/smctr-ssctr-valid.s
b/llvm/test/MC/RISCV/smctr-ssctr-valid.s
index 8bbd5a426b8ee..072231a9b546e 100644
--- a/llvm/test/MC/RISCV/smctr-ssctr-valid.s
+++ b/llvm/test/MC/RISCV/smctr-ssctr-valid.s
@@ -1,22 +1,22 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-smctr -M no-aliases
-show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+smctr -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-smctr -M no-aliases
-show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+smctr -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-ssctr -M no-aliases
-show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+ssctr -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-ssctr -M no-aliases
-show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+ssctr -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-smctr < %s \
-# RUN: | llvm-objdump --mattr=+experimental-smctr -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+smctr < %s \
+# RUN: | llvm-objdump --mattr=+smctr -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-smctr < %s \
-# RUN: | llvm-objdump --mattr=+experimental-smctr -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+smctr < %s \
+# RUN: | llvm-objdump --mattr=+smctr -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-ssctr < %s \
-# RUN: | llvm-objdump --mattr=+experimental-ssctr -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+ssctr < %s \
+# RUN: | llvm-objdump --mattr=+ssctr -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+experimental-ssctr < %s \
-# RUN: | llvm-objdump --mattr=+experimental-ssctr -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+ssctr < %s \
+# RUN: | llvm-objdump --mattr=+ssctr -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
# RUN: not llvm-mc -triple riscv32 -M no-aliases -show-encoding < %s 2>&1 \
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 319538eaea135..db58d95d2d82c 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1099,6 +1099,7 @@ R"(All available -march extensions for RISC-V
smcdeleg 1.0
smcntrpmf 1.0
smcsrind 1.0
+ smctr 1.0
smdbltrp 1.0
smepmp 1.0
smmpm 1.0
@@ -1111,6 +1112,7 @@ R"(All available -march extensions for RISC-V
sscofpmf 1.0
sscounterenw 1.0
sscsrind 1.0
+ ssctr 1.0
ssdbltrp 1.0
ssnpm 1.0
sspm 1.0
@@ -1185,8 +1187,6 @@ Experimental extensions
zvbc32e 0.7
zvkgs 0.7
zvqdotq 0.0
- smctr 1.0
- ssctr 1.0
svukte 0.3
xqccmp 0.3
xqcia 0.7
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