https://github.com/markbhasawut created
https://github.com/llvm/llvm-project/pull/157464
This PR updates the avg builtins to support constant expression handling, by
extending the VectorExprEvaluator::VisitCallExpr that handles elementwise
integer binop builtins.
Closes #155390
>From 6a34a55fead1ee1fe04419b95cb34de1c464d707 Mon Sep 17 00:00:00 2001
From: Bhasawut Singhaphan <bhasa...@gmail.com>
Date: Mon, 8 Sep 2025 15:51:33 +0700
Subject: [PATCH 1/2] [Clang][Headers][X86] Enable constexpr handling for
MMX/SSE/AVX/AVX512 avg intrinsics
Updates the avg builtins to support constant expression handling.
---
clang/include/clang/Basic/BuiltinsX86.td | 25 ++++++++++++++++--------
clang/lib/AST/ExprConstant.cpp | 8 ++++++++
2 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/clang/include/clang/Basic/BuiltinsX86.td
b/clang/include/clang/Basic/BuiltinsX86.td
index b4ff550d27279..499e67c3d6fff 100644
--- a/clang/include/clang/Basic/BuiltinsX86.td
+++ b/clang/include/clang/Basic/BuiltinsX86.td
@@ -93,8 +93,6 @@ let Attributes = [Const, NoThrow, RequiredVectorWidth<128>]
in {
}
let Features = "sse2" in {
- def pavgb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>,
_Vector<16, char>)">;
- def pavgw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8,
short>)">;
def packsswb128 : X86Builtin<"_Vector<16, char>(_Vector<8, short>,
_Vector<8, short>)">;
def packssdw128 : X86Builtin<"_Vector<8, short>(_Vector<4, int>,
_Vector<4, int>)">;
def packuswb128 : X86Builtin<"_Vector<16, char>(_Vector<8, short>,
_Vector<8, short>)">;
@@ -106,6 +104,10 @@ let Attributes = [Const, NoThrow,
RequiredVectorWidth<128>] in {
}
let Features = "sse2", Attributes = [NoThrow, Const, Constexpr,
RequiredVectorWidth<128>] in {
+ def pavgb128 : X86Builtin<"_Vector<16, unsigned char>(_Vector<16, unsigned
"
+ "char>, _Vector<16, unsigned char>)">;
+ def pavgw128 : X86Builtin<"_Vector<8, unsigned short>(_Vector<8, unsigned "
+ "short>, _Vector<8, unsigned short>)">;
def pmulhw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>,
_Vector<8, short>)">;
def pmulhuw128 : X86Builtin<"_Vector<8, unsigned short>(_Vector<8,
unsigned short>, _Vector<8, unsigned short>)">;
}
@@ -574,9 +576,8 @@ let Features = "avx2", Attributes = [NoThrow, Const,
RequiredVectorWidth<256>] i
def packssdw256 : X86Builtin<"_Vector<16, short>(_Vector<8, int>, _Vector<8,
int>)">;
def packuswb256 : X86Builtin<"_Vector<32, char>(_Vector<16, short>,
_Vector<16, short>)">;
def packusdw256 : X86Builtin<"_Vector<16, short>(_Vector<8, int>, _Vector<8,
int>)">;
- def palignr256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>,
_Vector<32, char>, _Constant int)">;
- def pavgb256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Vector<32,
char>)">;
- def pavgw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>,
_Vector<16, short>)">;
+ def palignr256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>, "
+ "_Vector<32, char>, _Constant int)">;
def pblendw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>,
_Vector<16, short>, _Constant int)">;
def phaddw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>,
_Vector<16, short>)">;
def phaddd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8,
int>)">;
@@ -618,6 +619,11 @@ let Features = "avx2", Attributes = [NoThrow, Const,
RequiredVectorWidth<256>] i
}
let Features = "avx2", Attributes = [NoThrow, Const, Constexpr,
RequiredVectorWidth<256>] in {
+ def pavgb256 : X86Builtin<"_Vector<32, unsigned char>(_Vector<32, unsigned "
+ "char>, _Vector<32, unsigned char>)">;
+ def pavgw256 : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, unsigned "
+ "short>, _Vector<16, unsigned short>)">;
+
def pblendvb256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>,
_Vector<32, char>, _Vector<32, char>)">;
def pmuldq256 : X86Builtin<"_Vector<4, long long int>(_Vector<8, int>,
_Vector<8, int>)">;
@@ -1306,9 +1312,8 @@ let Features = "avx512bw", Attributes = [NoThrow, Const,
RequiredVectorWidth<512
def packssdw512 : X86Builtin<"_Vector<32, short>(_Vector<16, int>,
_Vector<16, int>)">;
def packsswb512 : X86Builtin<"_Vector<64, char>(_Vector<32, short>,
_Vector<32, short>)">;
def packusdw512 : X86Builtin<"_Vector<32, short>(_Vector<16, int>,
_Vector<16, int>)">;
- def packuswb512 : X86Builtin<"_Vector<64, char>(_Vector<32, short>,
_Vector<32, short>)">;
- def pavgb512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64,
char>)">;
- def pavgw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>,
_Vector<32, short>)">;
+ def packuswb512
+ : X86Builtin<"_Vector<64, char>(_Vector<32, short>, _Vector<32,
short>)">;
def pshufb512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64,
char>)">;
}
@@ -1350,6 +1355,10 @@ let Features = "avx512bw", Attributes = [NoThrow, Const,
RequiredVectorWidth<512
}
let Features = "avx512bw", Attributes = [NoThrow, Const, Constexpr,
RequiredVectorWidth<512>] in {
+ def pavgb512 : X86Builtin<"_Vector<64, unsigned char>(_Vector<64, unsigned "
+ "char>, _Vector<64, unsigned char>)">;
+ def pavgw512 : X86Builtin<"_Vector<32, unsigned short>(_Vector<32, unsigned "
+ "short>, _Vector<32, unsigned short>)">;
def pmulhuw512 : X86Builtin<"_Vector<32, unsigned short>(_Vector<32,
unsigned short>, _Vector<32, unsigned short>)">;
def pmulhw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>,
_Vector<32, short>)">;
}
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index ca930737474df..1839b39b50d04 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -11694,6 +11694,14 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr
*E) {
return LHS.isSigned() ? LHS.ssub_sat(RHS) : LHS.usub_sat(RHS);
});
+ case clang::X86::BI____builtin_ia32_pavgb128:
+ case clang::X86::BI____builtin_ia32_pavgw128:
+ case clang::X86::BI____builtin_ia32_pavgb256:
+ case clang::X86::BI____builtin_ia32_pavgw256:
+ case clang::X86::BI____builtin_ia32_pavgb512:
+ case clang::X86::BI____builtin_ia32_pavgw512:
+ return EvaluateBinOpExpr(llvm::APIntOps::avgCeilU);
+
case clang::X86::BI__builtin_ia32_pmulhuw128:
case clang::X86::BI__builtin_ia32_pmulhuw256:
case clang::X86::BI__builtin_ia32_pmulhuw512:
>From 5c6fa2ef132bdd6f8ada871f09615a4a7b5cbfe7 Mon Sep 17 00:00:00 2001
From: Bhasawut Singhaphan <bhasa...@gmail.com>
Date: Mon, 8 Sep 2025 09:51:38 +0000
Subject: [PATCH 2/2] [clang][bytecode] Implement ia32_pavg* builtins
This PR is used for handling of the __builtin_ia32_pavg builtins inside
VectorExprEvaluator::VisitCallExpr.
---
clang/lib/AST/ByteCode/InterpBuiltin.cpp | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/clang/lib/AST/ByteCode/InterpBuiltin.cpp
b/clang/lib/AST/ByteCode/InterpBuiltin.cpp
index a0dcdace854b9..110c1977b00f0 100644
--- a/clang/lib/AST/ByteCode/InterpBuiltin.cpp
+++ b/clang/lib/AST/ByteCode/InterpBuiltin.cpp
@@ -3299,6 +3299,15 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC,
const CallExpr *Call,
return LHS.isSigned() ? LHS.ssub_sat(RHS) : LHS.usub_sat(RHS);
});
+ case clang::X86::BI____builtin_ia32_pavgb128:
+ case clang::X86::BI____builtin_ia32_pavgw128:
+ case clang::X86::BI____builtin_ia32_pavgb256:
+ case clang::X86::BI____builtin_ia32_pavgw256:
+ case clang::X86::BI____builtin_ia32_pavgb512:
+ case clang::X86::BI____builtin_ia32_pavgw512:
+ return interp__builtin_elementwise_int_binop(S, OpPC, Call,
+ llvm::APIntOps::avgCeilU);
+
case clang::X86::BI__builtin_ia32_pmulhuw128:
case clang::X86::BI__builtin_ia32_pmulhuw256:
case clang::X86::BI__builtin_ia32_pmulhuw512:
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