https://github.com/futog updated
https://github.com/llvm/llvm-project/pull/157835
>From 190b3abb0c629efab4727288bb87dccaa63003e9 Mon Sep 17 00:00:00 2001
From: Gergely Futo <gergely.f...@hightec-rt.com>
Date: Tue, 9 Sep 2025 15:03:16 +0200
Subject: [PATCH 1/2] [RISCV] Make "target-feature +i" explicit
Add "target-feature +i" for RV32I/RV64I.
Current behavior:
RV32E/RV64E: "target-feature +e" "target-feature -i"
RV32I/RV64I: "target-feature -e"
Adding "target-feature +i" explicitly makes the behavior consistent.
---
.../CodeGen/RISCV/riscv-func-attr-target.c | 24 +++++++++----------
.../RISCV/rvv-intrinsics-handcrafted/vlenb.c | 4 ++--
clang/test/Driver/riscv-cpus.c | 3 ++-
clang/test/Driver/riscv-default-features.c | 4 ++--
clang/test/Driver/riscv-features.c | 12 ++++++++++
llvm/lib/TargetParser/RISCVISAInfo.cpp | 5 ----
.../TargetParser/RISCVISAInfoTest.cpp | 13 +++++-----
7 files changed, 37 insertions(+), 28 deletions(-)
diff --git a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
index c5189d6aab28f..5e998b7f93ece 100644
--- a/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
+++ b/clang/test/CodeGen/RISCV/riscv-func-attr-target.c
@@ -80,16 +80,16 @@ int test_vsetvlmax_e64m1() {
}
//.
-// CHECK: attributes #0 = {
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zifencei,+zmmul,-relax,-zbb,-zfa"
}
-// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64"
"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
"tune-cpu"="generic-rv64" }
-// CHECK: attributes #2 = {
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa"
}
-// CHECK: attributes #3 = {
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+v,+zaamo,+zalrsc,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa"
}
+// CHECK: attributes #0 = {
{{.*}}"target-features"="+64bit,+a,+i,+m,+save-restore,+zaamo,+zalrsc,+zifencei,+zmmul,-relax,-zbb,-zfa"
}
+// CHECK: attributes #1 = { {{.*}}"target-cpu"="rocket-rv64"
"target-features"="+64bit,+a,+d,+f,+i,+m,+save-restore,+v,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
"tune-cpu"="generic-rv64" }
+// CHECK: attributes #2 = {
{{.*}}"target-features"="+64bit,+a,+i,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa"
}
+// CHECK: attributes #3 = {
{{.*}}"target-features"="+64bit,+a,+d,+f,+i,+m,+save-restore,+v,+zaamo,+zalrsc,+zbb,+zicond,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-relax,-zfa"
}
// Make sure we append negative features if we override the arch
-// CHECK: attributes #4 = {
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zca,+zcd,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
}
-// CHECK: attributes #5 = {
{{.*}}"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
}
-// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa"
}
-// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
}
-// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+c,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
}
-// CHECK: attributes #9 = {
{{.*}}"target-features"="+64bit,+a,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa"
}
-// CHECK: attributes #11 = {
{{.*}}"target-features"="+64bit,+a,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa"
}
-// CHECK: attributes #12 = {
{{.*}}"target-features"="+64bit,+a,+d,+f,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
}
+// CHECK: attributes #4 = {
{{.*}}"target-features"="+64bit,+a,+c,+d,+f,+i,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zca,+zcd,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
}
+// CHECK: attributes #5 = {
{{.*}}"target-features"="+64bit,+i,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
}
+// CHECK: attributes #6 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+i,+m,+save-restore,+zaamo,+zalrsc,+zbb,+zifencei,+zmmul,-relax,-zfa"
}
+// CHECK: attributes #7 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+i,+m,+save-restore,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
}
+// CHECK: attributes #8 = { {{.*}}"target-cpu"="sifive-u54"
"target-features"="+64bit,+a,+c,+d,+f,+i,+m,+save-restore,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,{{(-[[:alnum:]-]+)(,-[[:alnum:]-]+)*}}"
}
+// CHECK: attributes #9 = {
{{.*}}"target-features"="+64bit,+a,+i,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32x,+zvl32b,-relax,-zbb,-zfa"
}
+// CHECK: attributes #11 = {
{{.*}}"target-features"="+64bit,+a,+f,+i,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zvl32b,-relax,-zbb,-zfa"
}
+// CHECK: attributes #12 = {
{{.*}}"target-features"="+64bit,+a,+d,+f,+i,+m,+save-restore,+zaamo,+zalrsc,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl32b,+zvl64b,-relax,-zbb,-zfa"
}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
index 582d5fd812bc3..1210a7857806d 100644
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vlenb.c
@@ -21,10 +21,10 @@ unsigned long test_vlenb(void) {
return __riscv_vlenb();
}
//.
-// RV32: attributes #[[ATTR0:[0-9]+]] = { mustprogress nofree noinline
norecurse nosync nounwind willreturn memory(read) vscale_range(2,1024)
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+32bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
}
+// RV32: attributes #[[ATTR0:[0-9]+]] = { mustprogress nofree noinline
norecurse nosync nounwind willreturn memory(read) vscale_range(2,1024)
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+32bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
}
// RV32: attributes #[[ATTR1:[0-9]+]] = { mustprogress nocallback nofree
nosync nounwind willreturn memory(read) }
//.
-// RV64: attributes #[[ATTR0:[0-9]+]] = { mustprogress nofree noinline
norecurse nosync nounwind willreturn memory(read) vscale_range(2,1024)
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+64bit,+d,+f,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
}
+// RV64: attributes #[[ATTR0:[0-9]+]] = { mustprogress nofree noinline
norecurse nosync nounwind willreturn memory(read) vscale_range(2,1024)
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+64bit,+d,+f,+i,+v,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b"
}
// RV64: attributes #[[ATTR1:[0-9]+]] = { mustprogress nocallback nofree
nosync nounwind willreturn memory(read) }
//.
// RV32: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index ea0821cc39c45..a9c0db65af433 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -401,7 +401,8 @@
// -march overwrite -mcpu's default -march
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=sifive-e31
-march=rv32imc | FileCheck -check-prefix=MCPU-MARCH %s
-// MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature"
"+m" "-target-feature" "+c"
+// MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31"
+// MCPU-MARCH: "-target-feature" "+m" "-target-feature" "+c"
// MCPU-MARCH: "-target-abi" "ilp32"
// -march=unset erases previous march
diff --git a/clang/test/Driver/riscv-default-features.c
b/clang/test/Driver/riscv-default-features.c
index 4c3883c1cc118..f127f30297cf6 100644
--- a/clang/test/Driver/riscv-default-features.c
+++ b/clang/test/Driver/riscv-default-features.c
@@ -1,8 +1,8 @@
// RUN: %clang --target=riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck
%s -check-prefix=RV32
// RUN: %clang --target=riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck
%s -check-prefix=RV64
-// RV32: "target-features"="+32bit,+a,+c,+m,+relax,
-// RV64: "target-features"="+64bit,+a,+c,+m,+relax,
+// RV32: "target-features"="+32bit,+a,+c,+i,+m,+relax,
+// RV64: "target-features"="+64bit,+a,+c,+i,+m,+relax,
// Dummy function
int foo(void){
diff --git a/clang/test/Driver/riscv-features.c
b/clang/test/Driver/riscv-features.c
index 80dec2c71f985..1c8b52bd31997 100644
--- a/clang/test/Driver/riscv-features.c
+++ b/clang/test/Driver/riscv-features.c
@@ -1,3 +1,4 @@
+
// RUN: %clang --target=riscv32-unknown-elf -### %s -fsyntax-only 2>&1 |
FileCheck %s
// RUN: %clang --target=riscv64-unknown-elf -### %s -fsyntax-only 2>&1 |
FileCheck %s
// RUN: %clang --target=riscv64-linux-android -### %s -fsyntax-only 2>&1 |
FileCheck %s
-check-prefixes=ANDROID,DEFAULT,FAST-SCALAR-UNALIGNED-ACCESS,FAST-VECTOR-UNALIGNED-ACCESS
@@ -85,3 +86,14 @@
// FUCHSIA-SAME: "-target-feature" "+zbb"
// FUCHSIA-SAME: "-target-feature" "+zbs"
+
+// RUN: %clang --target=riscv32-unknown-elf -### -march=rv32i %s -fsyntax-only
2>&1 | FileCheck %s -check-prefix=RVI
+// RUN: %clang --target=riscv32-unknown-elf -### -march=rv64i %s -fsyntax-only
2>&1 | FileCheck %s -check-prefix=RVI
+// RUN: %clang --target=riscv32-unknown-elf -### -march=rv32e %s -fsyntax-only
2>&1 | FileCheck %s -check-prefix=RVE
+// RUN: %clang --target=riscv32-unknown-elf -### -march=rv64e %s -fsyntax-only
2>&1 | FileCheck %s -check-prefix=RVE
+
+// RVI: "-target-feature" "+i"
+// RVI-SAME: "-target-feature" "-e"
+
+// RVE: "-target-feature" "+e"
+// RVE-SAME: "-target-feature" "-i"
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp
b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 7617058aa102f..9268df29f5237 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -287,11 +287,6 @@ std::vector<std::string> RISCVISAInfo::toFeatures(bool
AddAllExtensions,
bool IgnoreUnknown) const {
std::vector<std::string> Features;
for (const auto &[ExtName, _] : Exts) {
- // i is a base instruction set, not an extension (see
- //
https://github.com/riscv/riscv-isa-manual/blob/main/src/naming.adoc#base-integer-isa)
- // and is not recognized in clang -cc1
- if (ExtName == "i")
- continue;
if (IgnoreUnknown && !isSupportedExtension(ExtName))
continue;
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index d10dcb683652a..febd06ea51739 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -809,7 +809,7 @@ TEST(ToFeatures,
IIsDroppedAndExperimentalExtensionsArePrefixed) {
RISCVISAInfo::parseArchString("rv64im_zalasr", true, false);
ASSERT_THAT_EXPECTED(MaybeISAInfo1, Succeeded());
EXPECT_THAT((*MaybeISAInfo1)->toFeatures(),
- ElementsAre("+m", "+zmmul", "+experimental-zalasr"));
+ ElementsAre("+i", "+m", "+zmmul", "+experimental-zalasr"));
auto MaybeISAInfo2 = RISCVISAInfo::parseArchString(
"rv32e_zalasr_xventanacondops", true, false);
@@ -822,7 +822,7 @@ TEST(ToFeatures, UnsupportedExtensionsAreDropped) {
auto MaybeISAInfo =
RISCVISAInfo::parseNormalizedArchString("rv64i2p0_m2p0_xmadeup1p0");
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
- EXPECT_THAT((*MaybeISAInfo)->toFeatures(), ElementsAre("+m"));
+ EXPECT_THAT((*MaybeISAInfo)->toFeatures(), ElementsAre("+i", "+m"));
}
TEST(ToFeatures, UnsupportedExtensionsAreKeptIfIgnoreUnknownIsFalse) {
@@ -830,7 +830,7 @@ TEST(ToFeatures,
UnsupportedExtensionsAreKeptIfIgnoreUnknownIsFalse) {
RISCVISAInfo::parseNormalizedArchString("rv64i2p0_m2p0_xmadeup1p0");
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
EXPECT_THAT((*MaybeISAInfo)->toFeatures(false, false),
- ElementsAre("+m", "+xmadeup"));
+ ElementsAre("+i", "+m", "+xmadeup"));
}
TEST(ToFeatures, AddAllExtensionsAddsNegativeExtensions) {
@@ -838,10 +838,11 @@ TEST(ToFeatures, AddAllExtensionsAddsNegativeExtensions) {
ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded());
auto Features = (*MaybeISAInfo)->toFeatures(true);
- EXPECT_GT(Features.size(), 1UL);
- EXPECT_EQ(Features.front(), "+m");
+ EXPECT_GT(Features.size(), 2UL);
+ EXPECT_EQ(Features[0], "+i");
+ EXPECT_EQ(Features[1], "+m");
// Every feature after should be a negative feature
- for (auto &NegativeExt : llvm::drop_begin(Features))
+ for (auto &NegativeExt : llvm::drop_begin(Features, 2))
EXPECT_TRUE(NegativeExt.substr(0, 1) == "-");
}
>From 428305a7b43a604d7f397090fb1151eec2781a57 Mon Sep 17 00:00:00 2001
From: Gergely Futo <gergely.f...@hightec-rt.com>
Date: Wed, 10 Sep 2025 14:43:16 +0200
Subject: [PATCH 2/2] Correct some tests
---
clang/test/Driver/riscv-cpus.c | 5 ++++-
flang/test/Driver/target-cpu-features.f90 | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index a9c0db65af433..88ec766ff6966 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -407,7 +407,10 @@
// -march=unset erases previous march
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -march=rv32imc -march=unset
-mcpu=sifive-e31 | FileCheck -check-prefix=MARCH-UNSET %s
-// MARCH-UNSET: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature"
"+m" "-target-feature" "+a" "-target-feature" "+c"
+// MARCH-UNSET: "-nostdsysteminc" "-target-cpu" "sifive-e31"
+// MARCH-UNSET: "-target-feature" "+m"
+// MARCH-UNSET: "-target-feature" "+a"
+// MARCH-UNSET: "-target-feature" "+c"
// MARCH-UNSET-SAME: "-target-abi" "ilp32"
// Check interaction between -mcpu and mtune, -mtune won't affect arch related
diff --git a/flang/test/Driver/target-cpu-features.f90
b/flang/test/Driver/target-cpu-features.f90
index 58ee670d46c51..92ad12de781f2 100644
--- a/flang/test/Driver/target-cpu-features.f90
+++ b/flang/test/Driver/target-cpu-features.f90
@@ -74,7 +74,7 @@
! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd"
"-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm"
"-target-feature" "-fsgsbase"
! CHECK-RV64: "-fc1" "-triple" "riscv64-unknown-linux-gnu"
-! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+m"
"-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
"-target-feature" "+c"
+! CHECK-RV64-SAME: "-target-cpu" "generic-rv64" "-target-feature" "+i"
"-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f"
"-target-feature" "+d" "-target-feature" "+c"
! CHECK-AMDGPU: "-fc1" "-triple" "amdgcn-amd-amdhsa"
! CHECK-AMDGPU-SAME: "-target-cpu" "gfx908"
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
