https://github.com/tclin914 updated https://github.com/llvm/llvm-project/pull/157014
>From 0e5927d231128105a9b228cc4dd7c0c18a4bdf4d Mon Sep 17 00:00:00 2001 From: Jim Lin <j...@andestech.com> Date: Fri, 29 Aug 2025 13:16:29 +0800 Subject: [PATCH 1/2] [RISCV] Implement MC support for Zvfofp8min extension This patch adds MC support for Zvfofp8min https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfofp8min.adoc. --- .../Driver/print-supported-extensions-riscv.c | 1 + .../test/Preprocessor/riscv-target-features.c | 9 +++++ llvm/docs/RISCVUsage.rst | 1 + llvm/docs/ReleaseNotes.md | 1 + llvm/lib/Target/RISCV/RISCVFeatures.td | 19 ++++++++-- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 + llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td | 3 +- .../Target/RISCV/RISCVInstrInfoZvfofp8min.td | 26 ++++++++++++++ llvm/lib/TargetParser/RISCVTargetParser.cpp | 2 +- llvm/test/CodeGen/RISCV/attributes.ll | 4 +++ llvm/test/CodeGen/RISCV/features-info.ll | 1 + llvm/test/MC/RISCV/attribute-arch.s | 3 ++ llvm/test/MC/RISCV/rvv/zvfbfmin.s | 8 ++--- llvm/test/MC/RISCV/rvv/zvfofp8min.s | 36 +++++++++++++++++++ .../TargetParser/RISCVISAInfoTest.cpp | 1 + 15 files changed, 107 insertions(+), 9 deletions(-) create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td create mode 100644 llvm/test/MC/RISCV/rvv/zvfofp8min.s diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index f619d32254d15..e67786dded67f 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -218,6 +218,7 @@ // CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions) // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) // CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support) +// CHECK-NEXT: zvfofp8min 0.21 'Zvfofp8min' (Vector OFP8 Converts) // CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography) // CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product) // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 0dcdb29445b4b..e7c0799b349ae 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -179,6 +179,7 @@ // CHECK-NOT: __riscv_ztso {{.*$}} // CHECK-NOT: __riscv_zvbc32e {{.*$}} // CHECK-NOT: __riscv_zvfbfa {{.*$}} +// CHECK-NOT: __riscv_zvfofp8min {{.*$}} // CHECK-NOT: __riscv_zvfbfmin {{.*$}} // CHECK-NOT: __riscv_zvfbfwma {{.*$}} // CHECK-NOT: __riscv_zvkgs {{.*$}} @@ -1569,6 +1570,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFA-EXT %s // CHECK-ZVFBFA-EXT: __riscv_zvfbfa 1000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32ifzvfofp8min0p21 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFOFP8MIN-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64ifzvfofp8min0p21 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFOFP8MIN-EXT %s +// CHECK-ZVFOFP8MIN-EXT: __riscv_zvfofp8min 21000{{$}} + // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_zve32x_zvbc32e0p7 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC32E-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index cfe090eddfa09..2ea571e12a277 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -236,6 +236,7 @@ on support follow. ``Zvfbfwma`` Supported ``Zvfh`` Supported ``Zvfhmin`` Supported + ``Zvfofp8min`` Assembly Support ``Zvkb`` Supported ``Zvkg`` Supported (`See note <#riscv-vector-crypto-note>`__) ``Zvkn`` Supported (`See note <#riscv-vector-crypto-note>`__) diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 3c3799321606a..c211844c62491 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -125,6 +125,7 @@ Changes to the RISC-V Backend * Ssctr and Smctr extensions are no longer experimental. * Add support for Zvfbfa (Additional BF16 vector compute support) * Adds experimental support for the 'Zibi` (Branch with Immediate) extension. +* Add support for Zvfofp8min (OFP8 conversion extension) Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index d0d82695edc9c..e947af5c62cf5 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -695,9 +695,6 @@ def HasStdExtZvfbfa : Predicate<"Subtarget->hasStdExtZvfbfa()">, def FeatureStdExtZvfbfmin : RISCVExtension<1, 0, "Vector BF16 Converts", [FeatureStdExtZve32f]>; -def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">, - AssemblerPredicate<(all_of FeatureStdExtZvfbfmin), - "'Zvfbfmin' (Vector BF16 Converts)">; def FeatureStdExtZvfbfwma : RISCVExtension<1, 0, "Vector BF16 widening mul-add", @@ -723,6 +720,22 @@ def HasStdExtZfhOrZvfh "'Zfh' (Half-Precision Floating-Point) or " "'Zvfh' (Vector Half-Precision Floating-Point)">; +def FeatureStdExtZvfofp8min + : RISCVExperimentalExtension<0, 21, + "Vector OFP8 Converts", [FeatureStdExtZve32f]>; +def HasStdExtZvfofp8min + : Predicate<"Subtarget->hasStdExtZvfofp8min()">, + AssemblerPredicate<(all_of FeatureStdExtZvfofp8min), + "'Zvfofp8min' (Vector OFP8 Converts)">; + +def HasStdExtZvfbfminOrZvfofp8min + : Predicate<"Subtarget->hasStdExtZvfbfmin() ||" + "Subtarget->hasStdExtZvfofp8min()">, + AssemblerPredicate<(any_of FeatureStdExtZvfbfmin, + FeatureStdExtZvfofp8min), + "'Zvfbfmin' (Vector BF16 Converts) or " + "'Zvfofp8min' (Vector OFP8 Converts)">; + // Vector Cryptography and Bitmanip Extensions def FeatureStdExtZvkb diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 3529d8f4799ab..47900cffa370c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2344,6 +2344,7 @@ include "RISCVInstrInfoZk.td" include "RISCVInstrInfoV.td" include "RISCVInstrInfoZvk.td" include "RISCVInstrInfoZvqdotq.td" +include "RISCVInstrInfoZvfofp8min.td" // Packed SIMD include "RISCVInstrInfoP.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td index cbeec9ba75f16..8f8fcb5d32feb 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td @@ -17,7 +17,8 @@ // Instructions //===----------------------------------------------------------------------===// -let Predicates = [HasStdExtZvfbfmin], Constraints = "@earlyclobber $vd", +let Predicates = [HasStdExtZvfbfminOrZvfofp8min], + Constraints = "@earlyclobber $vd", mayRaiseFPException = true in { let RVVConstraint = WidenCvt, DestEEW = EEWSEWx2 in defm VFWCVTBF16_F_F_V : VWCVTF_FV_VS2<"vfwcvtbf16.f.f.v", 0b010010, 0b01101>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td new file mode 100644 index 0000000000000..86cab697cbf55 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td @@ -0,0 +1,26 @@ +//===- RISCVInstrInfoZvfofp8min.td - 'Zvfofp8min' ----------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V instructions from the standard 'Zvfofp8min' +// extension, providing vector conversion instructions for OFP8. +// This version is still experimental as the 'Zvfofp8min' extension hasn't been +// ratified yet. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtZvfofp8min], Constraints = "@earlyclobber $vd", + mayRaiseFPException = true, Uses = [FRM, VL, VTYPE] in { + defm VFNCVTBF16_SAT_F_F_W + : VNCVTF_FV_VS2<"vfncvtbf16.sat.f.f.w", 0b010010, 0b11111>; + defm VFNCVT_F_F_Q : VNCVTF_FV_VS2<"vfncvt.f.f.q", 0b010010, 0b11001>; + defm VFNCVT_SAT_F_F_Q : VNCVTF_FV_VS2<"vfncvt.sat.f.f.q", 0b010010, 0b11011>; +} diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp index b53a1b95431aa..acf8e4cf7c6d2 100644 --- a/llvm/lib/TargetParser/RISCVTargetParser.cpp +++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -153,7 +153,7 @@ namespace RISCVVType { // // Bits | Name | Description // -----+------------+------------------------------------------------ -// 8 | altfmt | Alternative format for bf16 +// 8 | altfmt | Alternative format for bf16/ofp8 // 7 | vma | Vector mask agnostic // 6 | vta | Vector tail agnostic // 5:3 | vsew[2:0] | Standard element width (SEW) setting diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 154fb83172341..e58f93b231f3d 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -129,6 +129,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfa %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFA %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfofp8min %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFOFP8MIN %s ; RUN: llc -mtriple=riscv32 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV32ZALASR %s ; RUN: llc -mtriple=riscv32 -mattr=+zama16b %s -o - | FileCheck --check-prefixes=CHECK,RV32ZAMA16B %s @@ -277,6 +278,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfa %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFA %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfofp8min %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFOFP8MIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV64ZALASR %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s @@ -439,6 +441,7 @@ ; RV32ZVFBFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0" ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" +; RV32ZVFOFP8MIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p21_zvl32b1p0" ; RV32ZACAS: .attribute 5, "rv32i2p1_zaamo1p0_zacas1p0" ; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p1" ; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0" @@ -585,6 +588,7 @@ ; RV64ZVFBFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0" ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" +; RV64ZVFOFP8MIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p21_zvl32b1p0" ; RV64ZACAS: .attribute 5, "rv64i2p1_zaamo1p0_zacas1p0" ; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1" ; RV64ZALASRA: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalasr0p1_zalrsc1p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index a3b56c6fd3d77..fc77d6cb7c7be 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -57,6 +57,7 @@ ; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack). ; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements). ; CHECK-NEXT: experimental-zvfbfa - 'Zvfbfa' (Additional BF16 vector compute support). +; CHECK-NEXT: experimental-zvfofp8min - 'Zvfofp8min' (Vector OFP8 Converts). ; CHECK-NEXT: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography). ; CHECK-NEXT: experimental-zvqdotq - 'Zvqdotq' (Vector quad widening 4D Dot Product). ; CHECK-NEXT: f - 'F' (Single-Precision Floating-Point). diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index b2e2450b6771e..f7380f9e52bac 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -414,6 +414,9 @@ .attribute arch, "rv32i_zvfbfwma1p0" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" +.attribute arch, "rv32i_zvfofp8min0p21" +# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p21_zvl32b1p0" + .attribute arch, "rv32ia_zacas1p0" # CHECK: attribute 5, "rv32i2p1_a2p1_zaamo1p0_zacas1p0_zalrsc1p0" diff --git a/llvm/test/MC/RISCV/rvv/zvfbfmin.s b/llvm/test/MC/RISCV/rvv/zvfbfmin.s index c5f05c6be0df9..8a497f0c055e9 100644 --- a/llvm/test/MC/RISCV/rvv/zvfbfmin.s +++ b/llvm/test/MC/RISCV/rvv/zvfbfmin.s @@ -19,24 +19,24 @@ # CHECK-INST: vfncvtbf16.f.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x4e,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfofp8min' (Vector OFP8 Converts){{$}} # CHECK-UNKNOWN: 484e9457 <unknown> vfncvtbf16.f.f.w v8, v4, v0.t # CHECK-INST: vfncvtbf16.f.f.w v8, v4 # CHECK-ENCODING: [0x57,0x94,0x4e,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfofp8min' (Vector OFP8 Converts){{$}} # CHECK-UNKNOWN: 4a4e9457 <unknown> vfncvtbf16.f.f.w v8, v4 # CHECK-INST: vfwcvtbf16.f.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x46,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfofp8min' (Vector OFP8 Converts){{$}} # CHECK-UNKNOWN: 48469457 <unknown> vfwcvtbf16.f.f.v v8, v4, v0.t # CHECK-INST: vfwcvtbf16.f.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x46,0x4a] -# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts) or 'Zvfofp8min' (Vector OFP8 Converts){{$}} # CHECK-UNKNOWN: 4a469457 <unknown> vfwcvtbf16.f.f.v v8, v4 diff --git a/llvm/test/MC/RISCV/rvv/zvfofp8min.s b/llvm/test/MC/RISCV/rvv/zvfofp8min.s new file mode 100644 index 0000000000000..5ac24dfc100e5 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvfofp8min.s @@ -0,0 +1,36 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+experimental-zvfofp8min %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfofp8min %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-zvfofp8min - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+experimental-zvfofp8min %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+experimental-zvfofp8min %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfofp8min %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-zvfofp8min - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+experimental-zvfofp8min %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +# CHECK-INST: vfncvtbf16.sat.f.f.w v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x4f,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvfofp8min' (Vector OFP8 Converts){{$}} +# CHECK-UNKNOWN: 484f9457 <unknown> +vfncvtbf16.sat.f.f.w v8, v4, v0.t + +# CHECK-INST: vfncvt.f.f.q v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x4c,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvfofp8min' (Vector OFP8 Converts){{$}} +# CHECK-UNKNOWN: 484c9457 <unknown> +vfncvt.f.f.q v8, v4, v0.t + +# CHECK-INST: vfncvt.sat.f.f.q v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x4d,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvfofp8min' (Vector OFP8 Converts){{$}} +# CHECK-UNKNOWN: 484d9457 <unknown> +vfncvt.sat.f.f.q v8, v4, v0.t diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index e953c0d11590b..f03550a4afb15 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1190,6 +1190,7 @@ Experimental extensions zalasr 0.1 zvbc32e 0.7 zvfbfa 0.1 + zvfofp8min 0.21 zvkgs 0.7 zvqdotq 0.0 svukte 0.3 >From 81746296201c32e936b8b7cf35e25b3c820f8fe9 Mon Sep 17 00:00:00 2001 From: Jim Lin <j...@andestech.com> Date: Fri, 19 Sep 2025 13:37:33 +0800 Subject: [PATCH 2/2] Fix version to 0.2 --- clang/test/Driver/print-supported-extensions-riscv.c | 2 +- clang/test/Preprocessor/riscv-target-features.c | 6 +++--- llvm/lib/Target/RISCV/RISCVFeatures.td | 2 +- llvm/test/CodeGen/RISCV/attributes.ll | 4 ++-- llvm/test/MC/RISCV/attribute-arch.s | 4 ++-- llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index e67786dded67f..f5bef085c587e 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -218,7 +218,7 @@ // CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions) // CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements) // CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support) -// CHECK-NEXT: zvfofp8min 0.21 'Zvfofp8min' (Vector OFP8 Converts) +// CHECK-NEXT: zvfofp8min 0.2 'Zvfofp8min' (Vector OFP8 Converts) // CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography) // CHECK-NEXT: zvqdotq 0.0 'Zvqdotq' (Vector quad widening 4D Dot Product) // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index e7c0799b349ae..4090f3de3075d 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1571,12 +1571,12 @@ // CHECK-ZVFBFA-EXT: __riscv_zvfbfa 1000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32ifzvfofp8min0p21 -E -dM %s \ +// RUN: -march=rv32ifzvfofp8min0p2 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFOFP8MIN-EXT %s // RUN: %clang --target=riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64ifzvfofp8min0p21 -E -dM %s \ +// RUN: -march=rv64ifzvfofp8min0p2 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVFOFP8MIN-EXT %s -// CHECK-ZVFOFP8MIN-EXT: __riscv_zvfofp8min 21000{{$}} +// CHECK-ZVFOFP8MIN-EXT: __riscv_zvfofp8min 2000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_zve32x_zvbc32e0p7 -E -dM %s \ diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index e947af5c62cf5..8425cfb0bef82 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -721,7 +721,7 @@ def HasStdExtZfhOrZvfh "'Zvfh' (Vector Half-Precision Floating-Point)">; def FeatureStdExtZvfofp8min - : RISCVExperimentalExtension<0, 21, + : RISCVExperimentalExtension<0, 2, "Vector OFP8 Converts", [FeatureStdExtZve32f]>; def HasStdExtZvfofp8min : Predicate<"Subtarget->hasStdExtZvfofp8min()">, diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index e58f93b231f3d..ead255b929c7d 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -441,7 +441,7 @@ ; RV32ZVFBFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0" ; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" -; RV32ZVFOFP8MIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p21_zvl32b1p0" +; RV32ZVFOFP8MIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0" ; RV32ZACAS: .attribute 5, "rv32i2p1_zaamo1p0_zacas1p0" ; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p1" ; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0" @@ -588,7 +588,7 @@ ; RV64ZVFBFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfa0p1_zvl32b1p0" ; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0" ; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" -; RV64ZVFOFP8MIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p21_zvl32b1p0" +; RV64ZVFOFP8MIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0" ; RV64ZACAS: .attribute 5, "rv64i2p1_zaamo1p0_zacas1p0" ; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1" ; RV64ZALASRA: .attribute 5, "rv64i2p1_a2p1_zaamo1p0_zalasr0p1_zalrsc1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index f7380f9e52bac..b8cd6dea1ac81 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -414,8 +414,8 @@ .attribute arch, "rv32i_zvfbfwma1p0" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" -.attribute arch, "rv32i_zvfofp8min0p21" -# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p21_zvl32b1p0" +.attribute arch, "rv32i_zvfofp8min0p2" +# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfofp8min0p2_zvl32b1p0" .attribute arch, "rv32ia_zacas1p0" # CHECK: attribute 5, "rv32i2p1_a2p1_zaamo1p0_zacas1p0_zalrsc1p0" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index f03550a4afb15..b8efab6399779 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1190,7 +1190,7 @@ Experimental extensions zalasr 0.1 zvbc32e 0.7 zvfbfa 0.1 - zvfofp8min 0.21 + zvfofp8min 0.2 zvkgs 0.7 zvqdotq 0.0 svukte 0.3 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
