================
@@ -3027,6 +3027,29 @@ struct AMDGPUDeviceTy : public GenericDeviceTy,
AMDGenericDeviceTy {
return ((IsAPU || OMPX_ApuMaps) && IsXnackEnabled);
}
+ bool isAccessiblePtrImpl(const void *Ptr, size_t Size) override {
+ hsa_amd_pointer_info_t Info;
+ Info.size = sizeof(hsa_amd_pointer_info_t);
+
+ hsa_agent_t *Agents = nullptr;
+ uint32_t Count = 0;
+ hsa_status_t Status =
+ hsa_amd_pointer_info(Ptr, &Info, malloc, &Count, &Agents);
+
+ if (Status != HSA_STATUS_SUCCESS)
+ return false;
+
+ // Checks if the pointer is known by HSA and accessible by the device
+ for (uint32_t i = 0; i < Count; i++)
+ if (Agents[i].handle == getAgent().handle)
+ return Info.sizeInBytes >= Size;
+
+ // If the pointer is unknown to HSA it's assumed a host pointer
+ // in that case the device can access it on unified memory support is
+ // enabled
+ return IsXnackEnabled;
----------------
carlobertolli wrote:
Just a nit: there are GPUs that do not have xnack, but still have the ability
to access host memory. This behavior is fine for now, but we will have to
revisit based on GPU (later, not in this PR).
https://github.com/llvm/llvm-project/pull/138294
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