https://github.com/AditiRM updated https://github.com/llvm/llvm-project/pull/154715
>From 20acfd4109a453060f3678e536234de94012f19c Mon Sep 17 00:00:00 2001 From: AditiRM <[email protected]> Date: Thu, 21 Aug 2025 09:40:59 +0000 Subject: [PATCH 01/13] Implement frontend for bcd builtins --- clang/include/clang/Basic/BuiltinsPPC.def | 5 ++ clang/lib/Basic/Targets/PPC.cpp | 7 +++ clang/lib/Sema/SemaPPC.cpp | 4 ++ .../PowerPC/builtins-bcd-format-conversion.c | 56 +++++++++++++++++++ llvm/include/llvm/IR/IntrinsicsPowerPC.td | 29 +++++++++- 5 files changed, 99 insertions(+), 2 deletions(-) diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def index 79df84abd74f0..0e1789b507d5b 100644 --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -582,6 +582,11 @@ TARGET_BUILTIN(__builtin_ppc_bcdsub_p, "iiV16UcV16Uc", "", // P9 Binary-coded decimal (BCD) builtins. TARGET_BUILTIN(__builtin_ppc_bcdcopysign, "V16UcV16UcV16Uc", "", "power9-vector") TARGET_BUILTIN(__builtin_ppc_bcdsetsign, "V16UcV16UcUc", "t", "power9-vector") +TARGET_BUILTIN(__builtin_ppc_bcdshift, "V16UcV16UciUc", "t", "power9-vector") +TARGET_BUILTIN(__builtin_ppc_bcdshiftround, "V16UcV16UciUc", "t", "power9-vector") +TARGET_BUILTIN(__builtin_ppc_bcdtruncate, "V16UcV16UciUc", "t", "power9-vector") +TARGET_BUILTIN(__builtin_ppc_bcdunsignedtruncate, "V16UcV16Uci", "", "power9-vector") +TARGET_BUILTIN(__builtin_ppc_bcdunsignedshift, "V16UcV16Uci", "", "power9-vector") TARGET_BUILTIN(__builtin_ppc_national2packed, "V16UcV16UcUc", "t", "power9-vector") TARGET_BUILTIN(__builtin_ppc_packed2national, "V16UcV16Uc", "", "power9-vector") TARGET_BUILTIN(__builtin_ppc_packed2zoned, "V16UcV16UcUc", "t", "power9-vector") diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp index a6e1ad10568bb..a37a68ad91724 100644 --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -91,6 +91,13 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, static void defineXLCompatMacros(MacroBuilder &Builder) { Builder.defineMacro("__builtin_bcdcopysign", "__builtin_ppc_bcdcopysign"); Builder.defineMacro("__builtin_bcdsetsign", "__builtin_ppc_bcdsetsign"); + Builder.defineMacro("__builtin_bcdshift", "__builtin_ppc_bcdshift"); + Builder.defineMacro("__builtin_bcdshiftround", "__builtin_ppc_bcdshiftround"); + Builder.defineMacro("__builtin_bcdtruncate", "__builtin_ppc_bcdtruncate"); + Builder.defineMacro("__builtin_bcdunsignedtruncate", + "__builtin_ppc_bcdunsignedtruncate"); + Builder.defineMacro("__builtin_bcdunsignedshift", + "__builtin_ppc_bcdunsignedshift"); Builder.defineMacro("__builtin_national2packed", "__builtin_ppc_national2packed"); Builder.defineMacro("__builtin_packed2national", diff --git a/clang/lib/Sema/SemaPPC.cpp b/clang/lib/Sema/SemaPPC.cpp index 46d7372dd056b..85b084e9e2f24 100644 --- a/clang/lib/Sema/SemaPPC.cpp +++ b/clang/lib/Sema/SemaPPC.cpp @@ -113,6 +113,10 @@ bool SemaPPC::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, case PPC::BI__builtin_ppc_packed2zoned: case PPC::BI__builtin_ppc_zoned2packed: return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1); + case PPC::BI__builtin_ppc_bcdshiftround: + case PPC::BI__builtin_ppc_bcdtruncate: + case PPC::BI__builtin_ppc_bcdshift: + return SemaRef.BuiltinConstantArgRange(TheCall, 2, 0, 1); case PPC::BI__builtin_altivec_crypto_vshasigmaw: case PPC::BI__builtin_altivec_crypto_vshasigmad: return SemaRef.BuiltinConstantArgRange(TheCall, 1, 0, 1) || diff --git a/clang/test/CodeGen/PowerPC/builtins-bcd-format-conversion.c b/clang/test/CodeGen/PowerPC/builtins-bcd-format-conversion.c index 0aeb720e545ed..1698afa3b8b4f 100644 --- a/clang/test/CodeGen/PowerPC/builtins-bcd-format-conversion.c +++ b/clang/test/CodeGen/PowerPC/builtins-bcd-format-conversion.c @@ -27,3 +27,59 @@ vector unsigned char test_bcdsetsign_imm0(vector unsigned char a) { vector unsigned char test_bcdsetsign_imm1(vector unsigned char a) { return __builtin_ppc_bcdsetsign(a, '\1'); } + +// CHECK-LABEL: test_bcdshift_imm0 +// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdshift(<16 x i8> %a, i32 %b, i32 0) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +vector unsigned char test_bcdshift_imm0(vector unsigned char a, int b, unsigned char c){ + return __builtin_ppc_bcdshift(a,b,'\0'); +} + +// CHECK-LABEL: test_bcdshift_imm1 +// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdshift(<16 x i8> %a, i32 %b, i32 1) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +vector unsigned char test_bcdshift_imm1(vector unsigned char a, int b, unsigned char c){ + return __builtin_ppc_bcdshift(a,b,'\1'); +} + +// CHECK-LABEL: test_bcdshiftround_imm0 +// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8> %a, i32 %b, i32 0) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +vector unsigned char test_bcdshiftround_imm0(vector unsigned char a,int b, unsigned char c){ + return __builtin_ppc_bcdshiftround(a,b,'\0'); +} + +// CHECK-LABEL: test_bcdshiftround_imm1 +// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8> %a, i32 %b, i32 1) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +vector unsigned char test_bcdshiftround_imm1(vector unsigned char a,int b, unsigned char c){ + return __builtin_ppc_bcdshiftround(a,b,'\1'); +} + +// CHECK-LABEL: test_bcdtruncate_imm0 +// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8> %a, i32 %b, i32 0) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +vector unsigned char test_bcdtruncate_imm0(vector unsigned char a, int b, unsigned char c){ + return __builtin_ppc_bcdtruncate(a,b,'\0'); +} + +// CHECK-LABEL: test_bcdtruncate_imm1 +// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8> %a, i32 %b, i32 1) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +vector unsigned char test_bcdtruncate_imm1(vector unsigned char a, int b, unsigned char c){ + return __builtin_ppc_bcdtruncate(a,b,'\1'); +} + +// CHECK-LABEL: test_bcdunsignedtruncate +// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdunsignedtruncate(<16 x i8> %a, i32 %b) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +vector unsigned char test_bcdunsignedtruncate(vector unsigned char a, int b) { + return __builtin_ppc_bcdunsignedtruncate(a, b); +} + +// CHECK-LABEL: test_bcdunsignedshift +// CHECK: [[TMP0:%.*]] = tail call <16 x i8> @llvm.ppc.bcdunsignedshift(<16 x i8> %a, i32 %b) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +vector unsigned char test_bcdunsignedshift(vector unsigned char a, int b){ + return __builtin_ppc_bcdunsignedshift(a,b); +} \ No newline at end of file diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td index 94afa94bfb1ee..524dd90290311 100644 --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -680,8 +680,33 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". def int_ppc_bcdcopysign : ClangBuiltin<"__builtin_ppc_bcdcopysign">, DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_bcdsetsign : ClangBuiltin<"__builtin_ppc_bcdsetsign">, - DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], - [IntrNoMem, ImmArg<ArgIndex<1>>]>; + DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], + [IntrNoMem, ImmArg<ArgIndex<1>>]>; + + def int_ppc_bcdshift : ClangBuiltin<"__builtin_ppc_bcdshift">, + DefaultAttrsIntrinsic< + [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], + [IntrNoMem, ImmArg<ArgIndex<2>>]>; + + def int_ppc_bcdshiftround : ClangBuiltin<"__builtin_ppc_bcdshiftround">, + DefaultAttrsIntrinsic< + [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], + [IntrNoMem, ImmArg<ArgIndex<2>>]>; + + def int_ppc_bcdtruncate : ClangBuiltin<"__builtin_ppc_bcdtruncate">, + DefaultAttrsIntrinsic< + [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], + [IntrNoMem, ImmArg<ArgIndex<2>>]>; + + def int_ppc_bcdunsignedtruncate : ClangBuiltin<"__builtin_ppc_bcdunsignedtruncate">, + DefaultAttrsIntrinsic< + [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], + [IntrNoMem]>; + + def int_ppc_bcdunsignedshift : ClangBuiltin<"__builtin_ppc_bcdunsignedshift">, + DefaultAttrsIntrinsic< + [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], + [IntrNoMem]>; def int_ppc_bcdadd : ClangBuiltin<"__builtin_ppc_bcdadd">, DefaultAttrsIntrinsic< >From ba3ac3d6cf5aa2df7f61d5b4e0b262b91439d5c5 Mon Sep 17 00:00:00 2001 From: AditiRM <[email protected]> Date: Thu, 21 Aug 2025 10:22:54 +0000 Subject: [PATCH 02/13] Implement the backend lowering for bcd builtins --- llvm/include/llvm/IR/IntrinsicsPowerPC.td | 6 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 29 +++++ llvm/lib/Target/PowerPC/PPCISelLowering.h | 20 ++++ llvm/lib/Target/PowerPC/PPCInstrInfo.td | 40 +++++++ .../PowerPC/builtins-bcd-format-conversion.ll | 101 ++++++++++++++++++ 5 files changed, 193 insertions(+), 3 deletions(-) diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td index 524dd90290311..4055798e91074 100644 --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -680,9 +680,9 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". def int_ppc_bcdcopysign : ClangBuiltin<"__builtin_ppc_bcdcopysign">, DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; def int_ppc_bcdsetsign : ClangBuiltin<"__builtin_ppc_bcdsetsign">, - DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], - [IntrNoMem, ImmArg<ArgIndex<1>>]>; - + DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], + [IntrNoMem, ImmArg<ArgIndex<1>>]>; + def int_ppc_bcdshift : ClangBuiltin<"__builtin_ppc_bcdshift">, DefaultAttrsIntrinsic< [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index d6fe89a1904d3..4b274c2e42651 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1687,6 +1687,11 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { case PPCISD::STFIWX: return "PPCISD::STFIWX"; case PPCISD::VPERM: return "PPCISD::VPERM"; case PPCISD::XXSPLT: return "PPCISD::XXSPLT"; + case PPCISD::BCDSHIFT: return "PPCISD::BCDSHIFT"; + case PPCISD::BCDSHIFTROUND: return "PPCISD::BCDSHIFTROUND"; + case PPCISD::BCDTRUNC: return "PPCISD::BCDTRUNC"; + case PPCISD::BCDUTRUNC: return "PPCISD::BCDUTRUNC"; + case PPCISD::BCDUSHIFT: return "PPCISD::BCDUSHIFT"; case PPCISD::XXSPLTI_SP_TO_DP: return "PPCISD::XXSPLTI_SP_TO_DP"; case PPCISD::XXSPLTI32DX: @@ -11150,6 +11155,19 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, unsigned IntrinsicID = Op.getConstantOperandVal(0); SDLoc dl(Op); + + // Lowers BCD intrinsics with rounding operand + auto MapNodeWithSplatVector = [&](unsigned Opcode) -> SDValue { + SDValue SplatVal = DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); + return DAG.getNode(Opcode, dl, MVT::v16i8, + SplatVal, Op.getOperand(1), Op.getOperand(3)); + }; + // Lowers BCD intrinsics without rounding operand + auto MapNodeWithSplatVectorInt = [&](unsigned Opcode) -> SDValue { + SDValue SplatVal = DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); + return DAG.getNode(Opcode, dl, MVT::v16i8, + SplatVal, Op.getOperand(1)); + }; switch (IntrinsicID) { case Intrinsic::thread_pointer: @@ -11204,6 +11222,17 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 0); } + case Intrinsic:: ppc_bcdshift : + return MapNodeWithSplatVector(PPCISD::BCDSHIFT); + case Intrinsic:: ppc_bcdshiftround : + return MapNodeWithSplatVector(PPCISD::BCDSHIFTROUND); + case Intrinsic:: ppc_bcdtruncate : + return MapNodeWithSplatVector(PPCISD::BCDTRUNC); + case Intrinsic:: ppc_bcdunsignedtruncate : + return MapNodeWithSplatVectorInt(PPCISD::BCDUTRUNC); + case Intrinsic:: ppc_bcdunsignedshift : + return MapNodeWithSplatVectorInt(PPCISD::BCDUSHIFT); + case Intrinsic::ppc_rlwnm: { if (Op.getConstantOperandVal(3) == 0) return DAG.getConstant(0, dl, MVT::i32); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index 5e0d6bf184f20..0cc22cd62e5ba 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -97,6 +97,26 @@ namespace llvm { /// XXSPLT, + /// BCDSHIFT - The PPC bcdshift instruction + /// + BCDSHIFT, + + /// BCDSHIFTROUND - The PPC bcdshiftround instruction + /// + BCDSHIFTROUND, + + /// BCDTRUNC - The PPC bcdtruncate instruction + /// + BCDTRUNC, + + /// BCDUTRUNC - The PPC bcdunsigned truncate instruction + /// + BCDUTRUNC, + + /// BCDUSHIFT - The PPC bcdunsigned shift instruction + /// + BCDUSHIFT, + /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for /// converting immediate single precision numbers to double precision /// vector or scalar. diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index c2f91ce8e6b96..88819224fa7e9 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -50,6 +50,26 @@ def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, SDTCisVec<1>, SDTCisInt<2> ]>; +def SDT_PPCBcdShift : SDTypeProfile<1, 3, [ SDTCisVT<0, v16i8>, + SDTCisVT<1, v4i32>, SDTCisVT<2, v16i8>, SDTCisInt<3> +]>; + +def SDT_PPCBcdShiftRound : SDTypeProfile<1, 3, [ SDTCisVT<0, v16i8>, + SDTCisVT<1, v4i32>, SDTCisVT<2, v16i8>, SDTCisInt<3> +]>; + +def SDT_PPCBcdTrunc : SDTypeProfile<1, 3, [ SDTCisVT<0, v16i8>, + SDTCisVT<1, v4i32>, SDTCisVT<2, v16i8>, SDTCisInt<3> +]>; + +def SDT_PPCBcdUTrunc : SDTypeProfile<1, 2, [ SDTCisVT<0, v16i8>, + SDTCisVT<1, v4i32>, SDTCisVT<2, v16i8> +]>; + +def SDT_PPCBcdUShift : SDTypeProfile<1, 2, [ SDTCisVT<0, v16i8>, + SDTCisVT<1, v4i32>, SDTCisVT<2, v16i8> +]>; + def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>, SDTCisInt<1> ]>; @@ -249,6 +269,11 @@ def PPCpaddiDtprel : SDNode<"PPCISD::PADDI_DTPREL", SDTIntBinOp>; def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; +def PPCbcds : SDNode<"PPCISD::BCDSHIFT", SDT_PPCBcdShift, []>; +def PPCbcdsr : SDNode<"PPCISD::BCDSHIFTROUND", SDT_PPCBcdShiftRound, []>; +def PPCbcdtrunc : SDNode<"PPCISD::BCDTRUNC", SDT_PPCBcdTrunc, []>; +def PPCbcdutrunc : SDNode<"PPCISD::BCDUTRUNC", SDT_PPCBcdUTrunc, []>; +def PPCbcdus : SDNode<"PPCISD::BCDUSHIFT", SDT_PPCBcdUShift, []>; def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>; def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; @@ -3455,6 +3480,21 @@ include "PPCInstr64Bit.td" include "PPCInstrVSX.td" include "PPCInstrHTM.td" +def : Pat<(PPCbcds v4i32:$Shift, v16i8:$Src, i32:$PS), + (BCDS_rec $Shift, $Src, $PS)>; + +def : Pat<(PPCbcdsr v4i32:$ShiftRound, v16i8:$Src, i32:$PS), + (BCDSR_rec $ShiftRound, $Src, $PS)>; + +def : Pat<(PPCbcdtrunc v4i32:$Trunc, v16i8:$Src, i32:$PS), + (BCDTRUNC_rec $Trunc, $Src, $PS)>; + +def : Pat<(PPCbcdutrunc v4i32:$Trunc, v16i8:$Src), + (BCDUTRUNC_rec $Trunc, $Src)>; + +def : Pat<(PPCbcdus v4i32:$Shift, v16i8:$Src), + (BCDUS_rec $Shift, $Src)>; + def crnot : OutPatFrag<(ops node:$in), (CRNOT $in)>; def : Pat<(not i1:$in), diff --git a/llvm/test/CodeGen/PowerPC/builtins-bcd-format-conversion.ll b/llvm/test/CodeGen/PowerPC/builtins-bcd-format-conversion.ll index ede86254b1516..65dab378b9884 100644 --- a/llvm/test/CodeGen/PowerPC/builtins-bcd-format-conversion.ll +++ b/llvm/test/CodeGen/PowerPC/builtins-bcd-format-conversion.ll @@ -36,5 +36,106 @@ entry: ret <16 x i8> %0 } +define dso_local <16 x i8> @test_bcdshift_imm0(<16 x i8> noundef %a, i32 %b) { +; CHECK-LABEL: test_bcdshift_imm0: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]] +; CHECK-NEXT: bcds. v2, v3, v2, 0 +; CHECK-NEXT: blr + +entry: + %0 = tail call <16 x i8> @llvm.ppc.bcdshift(<16 x i8> %a, i32 %b, i32 0) + ret <16 x i8> %0 +} + +define dso_local <16 x i8> @test_bcdshift_imm1(<16 x i8> noundef %a, i32 %b) { +; CHECK-LABEL: test_bcdshift_imm1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]] +; CHECK-NEXT: bcds. v2, v3, v2, 1 +; CHECK-NEXT: blr + +entry: + %0 = tail call <16 x i8> @llvm.ppc.bcdshift(<16 x i8> %a, i32 %b, i32 1) + ret <16 x i8> %0 +} + +define dso_local <16 x i8> @test_bcdshiftround_imm0(<16 x i8> noundef %a, i32 %b) { +; CHECK-LABEL: test_bcdshiftround_imm0: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]] +; CHECK-NEXT: bcdsr. v2, v3, v2, 0 +; CHECK-NEXT: blr + +entry: + %0 = tail call <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8> %a, i32 %b, i32 0) + ret <16 x i8> %0 +} + +define dso_local <16 x i8> @test_bcdshiftround_imm1(<16 x i8> noundef %a, i32 %b) { +; CHECK-LABEL: test_bcdshiftround_imm1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]] +; CHECK-NEXT: bcdsr. v2, v3, v2, 1 +; CHECK-NEXT: blr + +entry: + %0 = tail call <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8> %a, i32 %b, i32 1) + ret <16 x i8> %0 +} + +define dso_local <16 x i8> @test_bcdtruncate_imm0(<16 x i8> noundef %a, i32 %b) { +; CHECK-LABEL: test_bcdtruncate_imm0: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]] +; CHECK-NEXT: bcdtrunc. v2, v3, v2, 0 +; CHECK-NEXT: blr + +entry: + %0 = tail call <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8> %a, i32 %b, i32 0) + ret <16 x i8> %0 +} + +define dso_local <16 x i8> @test_bcdtruncate_imm1(<16 x i8> noundef %a, i32 %b) { +; CHECK-LABEL: test_bcdtruncate_imm1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]] +; CHECK-NEXT: bcdtrunc. v2, v3, v2, 1 +; CHECK-NEXT: blr + +entry: + %0 = tail call <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8> %a, i32 %b, i32 1) + ret <16 x i8> %0 +} + +define dso_local <16 x i8> @test_bcdunsignedtruncate(<16 x i8> noundef %a, i32 %b) { +; CHECK-LABEL: test_bcdunsignedtruncate: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]] +; CHECK-NEXT: bcdutrunc. v2, v3, v2 +; CHECK-NEXT: blr + +entry: + %0 = tail call <16 x i8> @llvm.ppc.bcdunsignedtruncate(<16 x i8> %a, i32 %b) + ret <16 x i8> %0 +} + +define dso_local <16 x i8> @test_bcdunsignedshift(<16 x i8> noundef %a, i32 %b) { +; CHECK-LABEL: test_bcdunsignedshift: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]] +; CHECK-NEXT: bcdus. v2, v3, v2 +; CHECK-NEXT: blr + +entry: + %0 = tail call <16 x i8> @llvm.ppc.bcdunsignedshift(<16 x i8> %a, i32 %b) + ret <16 x i8> %0 +} + declare <16 x i8> @llvm.ppc.bcdcopysign(<16 x i8>, <16 x i8>) declare <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8>, i32) +declare <16 x i8> @llvm.ppc.bcdshift(<16 x i8>, i32, i32) +declare <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8>, i32, i32) +declare <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8>, i32, i32) +declare <16 x i8> @llvm.ppc.bcdunsignedtruncate(<16 x i8>, i32) +declare <16 x i8> @llvm.ppc.bcdunsignedshift(<16 x i8>, i32) >From 3fc6ed7e66adb655263cec71d00c801bff7849b6 Mon Sep 17 00:00:00 2001 From: AditiRM <[email protected]> Date: Thu, 21 Aug 2025 10:28:10 +0000 Subject: [PATCH 03/13] [nit] fix spacing issue --- llvm/include/llvm/IR/IntrinsicsPowerPC.td | 50 +++++++++++------------ 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td index 4055798e91074..ce177ec6a4c12 100644 --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -682,31 +682,31 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.". def int_ppc_bcdsetsign : ClangBuiltin<"__builtin_ppc_bcdsetsign">, DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<1>>]>; - - def int_ppc_bcdshift : ClangBuiltin<"__builtin_ppc_bcdshift">, - DefaultAttrsIntrinsic< - [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], - [IntrNoMem, ImmArg<ArgIndex<2>>]>; - - def int_ppc_bcdshiftround : ClangBuiltin<"__builtin_ppc_bcdshiftround">, - DefaultAttrsIntrinsic< - [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], - [IntrNoMem, ImmArg<ArgIndex<2>>]>; - - def int_ppc_bcdtruncate : ClangBuiltin<"__builtin_ppc_bcdtruncate">, - DefaultAttrsIntrinsic< - [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], - [IntrNoMem, ImmArg<ArgIndex<2>>]>; - - def int_ppc_bcdunsignedtruncate : ClangBuiltin<"__builtin_ppc_bcdunsignedtruncate">, - DefaultAttrsIntrinsic< - [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], - [IntrNoMem]>; - - def int_ppc_bcdunsignedshift : ClangBuiltin<"__builtin_ppc_bcdunsignedshift">, - DefaultAttrsIntrinsic< - [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], - [IntrNoMem]>; + + def int_ppc_bcdshift : ClangBuiltin<"__builtin_ppc_bcdshift">, + DefaultAttrsIntrinsic< + [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], + [IntrNoMem, ImmArg<ArgIndex<2>>]>; + + def int_ppc_bcdshiftround : ClangBuiltin<"__builtin_ppc_bcdshiftround">, + DefaultAttrsIntrinsic< + [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], + [IntrNoMem, ImmArg<ArgIndex<2>>]>; + + def int_ppc_bcdtruncate : ClangBuiltin<"__builtin_ppc_bcdtruncate">, + DefaultAttrsIntrinsic< + [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty], + [IntrNoMem, ImmArg<ArgIndex<2>>]>; + + def int_ppc_bcdunsignedtruncate : ClangBuiltin<"__builtin_ppc_bcdunsignedtruncate">, + DefaultAttrsIntrinsic< + [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], + [IntrNoMem]>; + + def int_ppc_bcdunsignedshift : ClangBuiltin<"__builtin_ppc_bcdunsignedshift">, + DefaultAttrsIntrinsic< + [llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], + [IntrNoMem]>; def int_ppc_bcdadd : ClangBuiltin<"__builtin_ppc_bcdadd">, DefaultAttrsIntrinsic< >From 9243d3c7adf8373754707f336529a2d92f215936 Mon Sep 17 00:00:00 2001 From: AditiRM <[email protected]> Date: Thu, 21 Aug 2025 10:39:08 +0000 Subject: [PATCH 04/13] [nit] clang-format resolve --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 33 +++++++++++++-------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 4b274c2e42651..ff1d4bafbb562 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1687,11 +1687,16 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { case PPCISD::STFIWX: return "PPCISD::STFIWX"; case PPCISD::VPERM: return "PPCISD::VPERM"; case PPCISD::XXSPLT: return "PPCISD::XXSPLT"; - case PPCISD::BCDSHIFT: return "PPCISD::BCDSHIFT"; - case PPCISD::BCDSHIFTROUND: return "PPCISD::BCDSHIFTROUND"; - case PPCISD::BCDTRUNC: return "PPCISD::BCDTRUNC"; - case PPCISD::BCDUTRUNC: return "PPCISD::BCDUTRUNC"; - case PPCISD::BCDUSHIFT: return "PPCISD::BCDUSHIFT"; + case PPCISD::BCDSHIFT: + return "PPCISD::BCDSHIFT"; + case PPCISD::BCDSHIFTROUND: + return "PPCISD::BCDSHIFTROUND"; + case PPCISD::BCDTRUNC: + return "PPCISD::BCDTRUNC"; + case PPCISD::BCDUTRUNC: + return "PPCISD::BCDUTRUNC"; + case PPCISD::BCDUSHIFT: + return "PPCISD::BCDUSHIFT"; case PPCISD::XXSPLTI_SP_TO_DP: return "PPCISD::XXSPLTI_SP_TO_DP"; case PPCISD::XXSPLTI32DX: @@ -11155,16 +11160,18 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, unsigned IntrinsicID = Op.getConstantOperandVal(0); SDLoc dl(Op); - + // Lowers BCD intrinsics with rounding operand auto MapNodeWithSplatVector = [&](unsigned Opcode) -> SDValue { - SDValue SplatVal = DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); + SDValue SplatVal = + DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); return DAG.getNode(Opcode, dl, MVT::v16i8, SplatVal, Op.getOperand(1), Op.getOperand(3)); }; // Lowers BCD intrinsics without rounding operand auto MapNodeWithSplatVectorInt = [&](unsigned Opcode) -> SDValue { - SDValue SplatVal = DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); + SDValue SplatVal = + DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); return DAG.getNode(Opcode, dl, MVT::v16i8, SplatVal, Op.getOperand(1)); }; @@ -11222,15 +11229,15 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 0); } - case Intrinsic:: ppc_bcdshift : + case Intrinsic:: ppc_bcdshift: return MapNodeWithSplatVector(PPCISD::BCDSHIFT); - case Intrinsic:: ppc_bcdshiftround : + case Intrinsic:: ppc_bcdshiftround: return MapNodeWithSplatVector(PPCISD::BCDSHIFTROUND); - case Intrinsic:: ppc_bcdtruncate : + case Intrinsic:: ppc_bcdtruncate: return MapNodeWithSplatVector(PPCISD::BCDTRUNC); - case Intrinsic:: ppc_bcdunsignedtruncate : + case Intrinsic:: ppc_bcdunsignedtruncate: return MapNodeWithSplatVectorInt(PPCISD::BCDUTRUNC); - case Intrinsic:: ppc_bcdunsignedshift : + case Intrinsic:: ppc_bcdunsignedshift: return MapNodeWithSplatVectorInt(PPCISD::BCDUSHIFT); case Intrinsic::ppc_rlwnm: { >From 632be8553631fe0d767d081d2f244e599553b42b Mon Sep 17 00:00:00 2001 From: AditiRM <[email protected]> Date: Thu, 21 Aug 2025 10:49:47 +0000 Subject: [PATCH 05/13] [nit] clang-format resolve --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index ff1d4bafbb562..ba058f3985924 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -11164,16 +11164,15 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, // Lowers BCD intrinsics with rounding operand auto MapNodeWithSplatVector = [&](unsigned Opcode) -> SDValue { SDValue SplatVal = - DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); - return DAG.getNode(Opcode, dl, MVT::v16i8, - SplatVal, Op.getOperand(1), Op.getOperand(3)); + DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); + return DAG.getNode(Opcode, dl, MVT::v16i8, SplatVal, Op.getOperand(1), + Op.getOperand(3)); }; // Lowers BCD intrinsics without rounding operand auto MapNodeWithSplatVectorInt = [&](unsigned Opcode) -> SDValue { SDValue SplatVal = - DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); - return DAG.getNode(Opcode, dl, MVT::v16i8, - SplatVal, Op.getOperand(1)); + DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); + return DAG.getNode(Opcode, dl, MVT::v16i8, SplatVal, Op.getOperand(1)); }; switch (IntrinsicID) { @@ -11229,15 +11228,15 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 0); } - case Intrinsic:: ppc_bcdshift: + case Intrinsic::ppc_bcdshift: return MapNodeWithSplatVector(PPCISD::BCDSHIFT); - case Intrinsic:: ppc_bcdshiftround: + case Intrinsic::ppc_bcdshiftround: return MapNodeWithSplatVector(PPCISD::BCDSHIFTROUND); - case Intrinsic:: ppc_bcdtruncate: + case Intrinsic::ppc_bcdtruncate: return MapNodeWithSplatVector(PPCISD::BCDTRUNC); - case Intrinsic:: ppc_bcdunsignedtruncate: + case Intrinsic::ppc_bcdunsignedtruncate: return MapNodeWithSplatVectorInt(PPCISD::BCDUTRUNC); - case Intrinsic:: ppc_bcdunsignedshift: + case Intrinsic::ppc_bcdunsignedshift: return MapNodeWithSplatVectorInt(PPCISD::BCDUSHIFT); case Intrinsic::ppc_rlwnm: { >From dc78877c9d5c8f274ffc106df8c464d42c41c449 Mon Sep 17 00:00:00 2001 From: AditiRM <[email protected]> Date: Thu, 21 Aug 2025 11:02:42 +0000 Subject: [PATCH 06/13] [nit] clang-format resolve --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index ba058f3985924..343964a1b1576 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -11163,16 +11163,16 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, // Lowers BCD intrinsics with rounding operand auto MapNodeWithSplatVector = [&](unsigned Opcode) -> SDValue { - SDValue SplatVal = - DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); - return DAG.getNode(Opcode, dl, MVT::v16i8, SplatVal, Op.getOperand(1), + SDValue SplatVal = + DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); + return DAG.getNode(Opcode, dl, MVT::v16i8, SplatVal, Op.getOperand(1), Op.getOperand(3)); }; // Lowers BCD intrinsics without rounding operand auto MapNodeWithSplatVectorInt = [&](unsigned Opcode) -> SDValue { - SDValue SplatVal = - DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); - return DAG.getNode(Opcode, dl, MVT::v16i8, SplatVal, Op.getOperand(1)); + SDValue SplatVal = + DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); + return DAG.getNode(Opcode, dl, MVT::v16i8, SplatVal, Op.getOperand(1)); }; switch (IntrinsicID) { >From e2eddfd2ac0d4879979deeb81a1b9ee2c02520fb Mon Sep 17 00:00:00 2001 From: AditiRM <[email protected]> Date: Fri, 22 Aug 2025 05:47:30 +0000 Subject: [PATCH 07/13] [nit] clang-format changes --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 343964a1b1576..e5b3b53440a8e 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -11164,14 +11164,14 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, // Lowers BCD intrinsics with rounding operand auto MapNodeWithSplatVector = [&](unsigned Opcode) -> SDValue { SDValue SplatVal = - DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); + DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); return DAG.getNode(Opcode, dl, MVT::v16i8, SplatVal, Op.getOperand(1), - Op.getOperand(3)); + Op.getOperand(3)); }; // Lowers BCD intrinsics without rounding operand auto MapNodeWithSplatVectorInt = [&](unsigned Opcode) -> SDValue { SDValue SplatVal = - DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); + DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); return DAG.getNode(Opcode, dl, MVT::v16i8, SplatVal, Op.getOperand(1)); }; >From a519e5a6a73e731c647bf12294f6829c8018e5e9 Mon Sep 17 00:00:00 2001 From: AditiRM <[email protected]> Date: Fri, 22 Aug 2025 05:51:48 +0000 Subject: [PATCH 08/13] [nit] clang-format changes --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index e5b3b53440a8e..4f5e7cfc334c3 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -11166,7 +11166,7 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SDValue SplatVal = DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); return DAG.getNode(Opcode, dl, MVT::v16i8, SplatVal, Op.getOperand(1), - Op.getOperand(3)); + Op.getOperand(3)); }; // Lowers BCD intrinsics without rounding operand auto MapNodeWithSplatVectorInt = [&](unsigned Opcode) -> SDValue { >From 2d5e5f4d42b09668f1b5218baef03b4ee32faa06 Mon Sep 17 00:00:00 2001 From: AditiRM <[email protected]> Date: Mon, 29 Sep 2025 08:39:28 +0000 Subject: [PATCH 09/13] Update the description and optimize the function --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 43 ++++++++++----------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 4f5e7cfc334c3..f75da30629e86 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -11160,19 +11160,18 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, unsigned IntrinsicID = Op.getConstantOperandVal(0); SDLoc dl(Op); - - // Lowers BCD intrinsics with rounding operand - auto MapNodeWithSplatVector = [&](unsigned Opcode) -> SDValue { - SDValue SplatVal = - DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); - return DAG.getNode(Opcode, dl, MVT::v16i8, SplatVal, Op.getOperand(1), - Op.getOperand(3)); - }; - // Lowers BCD intrinsics without rounding operand - auto MapNodeWithSplatVectorInt = [&](unsigned Opcode) -> SDValue { + // Note: BCD instructions expect the immediate operand in vector form (v4i32), + // but the builtin provides it as a scalar. To satisfy the instruction encoding, + // we splat the scalar across all lanes using SPLAT_VECTOR. + auto MapNodeWithSplatVector = [&](unsigned Opcode, + std::initializer_list<SDValue> + ExtraOps = {}) -> SDValue { SDValue SplatVal = - DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); - return DAG.getNode(Opcode, dl, MVT::v16i8, SplatVal, Op.getOperand(1)); + DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); + + SmallVector<SDValue, 4> Ops{SplatVal, Op.getOperand(1)}; + Ops.append(ExtraOps.begin(), ExtraOps.end()); + return DAG.getNode(Opcode, dl, MVT::v16i8, Ops); }; switch (IntrinsicID) { @@ -11228,16 +11227,16 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 0); } - case Intrinsic::ppc_bcdshift: - return MapNodeWithSplatVector(PPCISD::BCDSHIFT); - case Intrinsic::ppc_bcdshiftround: - return MapNodeWithSplatVector(PPCISD::BCDSHIFTROUND); - case Intrinsic::ppc_bcdtruncate: - return MapNodeWithSplatVector(PPCISD::BCDTRUNC); - case Intrinsic::ppc_bcdunsignedtruncate: - return MapNodeWithSplatVectorInt(PPCISD::BCDUTRUNC); - case Intrinsic::ppc_bcdunsignedshift: - return MapNodeWithSplatVectorInt(PPCISD::BCDUSHIFT); +case Intrinsic::ppc_bcdshift: + return MapNodeWithSplatVector(PPCISD::BCDSHIFT, {Op.getOperand(3)}); +case Intrinsic::ppc_bcdshiftround: + return MapNodeWithSplatVector(PPCISD::BCDSHIFTROUND, {Op.getOperand(3)}); +case Intrinsic::ppc_bcdtruncate: + return MapNodeWithSplatVector(PPCISD::BCDTRUNC, {Op.getOperand(3)}); +case Intrinsic::ppc_bcdunsignedtruncate: + return MapNodeWithSplatVector(PPCISD::BCDUTRUNC); +case Intrinsic::ppc_bcdunsignedshift: + return MapNodeWithSplatVector(PPCISD::BCDUSHIFT); case Intrinsic::ppc_rlwnm: { if (Op.getConstantOperandVal(3) == 0) >From d19969ebbdd8c72e81b1cc72158a407f67b0abb4 Mon Sep 17 00:00:00 2001 From: AditiRM <[email protected]> Date: Mon, 29 Sep 2025 08:58:34 +0000 Subject: [PATCH 10/13] fix clang format errors --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 27 +++++++++++---------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index f75da30629e86..28fcd0ac2fdb1 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -11163,9 +11163,10 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, // Note: BCD instructions expect the immediate operand in vector form (v4i32), // but the builtin provides it as a scalar. To satisfy the instruction encoding, // we splat the scalar across all lanes using SPLAT_VECTOR. - auto MapNodeWithSplatVector = [&](unsigned Opcode, - std::initializer_list<SDValue> - ExtraOps = {}) -> SDValue { + auto MapNodeWithSplatVector = + [&](unsigned Opcode, + std::initializer_list<SDValue> ExtraOps = {}) -> SDValue { + SDValue SplatVal = DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); @@ -11227,16 +11228,16 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, 0); } -case Intrinsic::ppc_bcdshift: - return MapNodeWithSplatVector(PPCISD::BCDSHIFT, {Op.getOperand(3)}); -case Intrinsic::ppc_bcdshiftround: - return MapNodeWithSplatVector(PPCISD::BCDSHIFTROUND, {Op.getOperand(3)}); -case Intrinsic::ppc_bcdtruncate: - return MapNodeWithSplatVector(PPCISD::BCDTRUNC, {Op.getOperand(3)}); -case Intrinsic::ppc_bcdunsignedtruncate: - return MapNodeWithSplatVector(PPCISD::BCDUTRUNC); -case Intrinsic::ppc_bcdunsignedshift: - return MapNodeWithSplatVector(PPCISD::BCDUSHIFT); + case Intrinsic::ppc_bcdshift: + return MapNodeWithSplatVector(PPCISD::BCDSHIFT, {Op.getOperand(3)}); + case Intrinsic::ppc_bcdshiftround: + return MapNodeWithSplatVector(PPCISD::BCDSHIFTROUND, {Op.getOperand(3)}); + case Intrinsic::ppc_bcdtruncate: + return MapNodeWithSplatVector(PPCISD::BCDTRUNC, {Op.getOperand(3)}); + case Intrinsic::ppc_bcdunsignedtruncate: + return MapNodeWithSplatVector(PPCISD::BCDUTRUNC); + case Intrinsic::ppc_bcdunsignedshift: + return MapNodeWithSplatVector(PPCISD::BCDUSHIFT); case Intrinsic::ppc_rlwnm: { if (Op.getConstantOperandVal(3) == 0) >From 3b92316bfd2322cb32d5b5c5523b453403d91049 Mon Sep 17 00:00:00 2001 From: AditiRM <[email protected]> Date: Mon, 29 Sep 2025 09:39:19 +0000 Subject: [PATCH 11/13] fix clang format errors --- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 28fcd0ac2fdb1..d91e660a6ebde 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -11161,14 +11161,13 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SDLoc dl(Op); // Note: BCD instructions expect the immediate operand in vector form (v4i32), - // but the builtin provides it as a scalar. To satisfy the instruction encoding, - // we splat the scalar across all lanes using SPLAT_VECTOR. + // but the builtin provides it as a scalar. To satisfy the instruction + // encoding, we splat the scalar across all lanes using SPLAT_VECTOR. auto MapNodeWithSplatVector = - [&](unsigned Opcode, - std::initializer_list<SDValue> ExtraOps = {}) -> SDValue { - + [&](unsigned Opcode, + std::initializer_list<SDValue> ExtraOps = {}) -> SDValue { SDValue SplatVal = - DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); + DAG.getNode(ISD::SPLAT_VECTOR, dl, MVT::v4i32, Op.getOperand(2)); SmallVector<SDValue, 4> Ops{SplatVal, Op.getOperand(1)}; Ops.append(ExtraOps.begin(), ExtraOps.end()); >From ed0a89fcec858d5817826e38edf6e40ad2491d9c Mon Sep 17 00:00:00 2001 From: AditiRM <[email protected]> Date: Mon, 6 Oct 2025 07:24:25 +0000 Subject: [PATCH 12/13] Move BCD patterns from PPCInstrInfo.td to PPCInstrAltivec.td --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 16 ++++++++++++++++ llvm/lib/Target/PowerPC/PPCInstrInfo.td | 15 --------------- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index 79fe12e8e4b49..b1cdc0e36ea94 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -1645,6 +1645,22 @@ def BCDSR_rec : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>; def BCDTRUNC_rec : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>; def BCDUTRUNC_rec : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>; +// Patterns mapping BCD DAG nodes to machine instructions +def : Pat<(PPCbcds v4i32:$Shift, v16i8:$Src, i32:$PS), + (BCDS_rec $Shift, $Src, $PS)>; + +def : Pat<(PPCbcdsr v4i32:$ShiftRound, v16i8:$Src, i32:$PS), + (BCDSR_rec $ShiftRound, $Src, $PS)>; + +def : Pat<(PPCbcdtrunc v4i32:$Trunc, v16i8:$Src, i32:$PS), + (BCDTRUNC_rec $Trunc, $Src, $PS)>; + +def : Pat<(PPCbcdutrunc v4i32:$Trunc, v16i8:$Src), + (BCDUTRUNC_rec $Trunc, $Src)>; + +def : Pat<(PPCbcdus v4i32:$Shift, v16i8:$Src), + (BCDUS_rec $Shift, $Src)>; + // Absolute Difference def VABSDUB : VXForm_1<1027, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), "vabsdub $VD, $VA, $VB", IIC_VecGeneral, diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 88819224fa7e9..ddd982d75ef0c 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -3480,21 +3480,6 @@ include "PPCInstr64Bit.td" include "PPCInstrVSX.td" include "PPCInstrHTM.td" -def : Pat<(PPCbcds v4i32:$Shift, v16i8:$Src, i32:$PS), - (BCDS_rec $Shift, $Src, $PS)>; - -def : Pat<(PPCbcdsr v4i32:$ShiftRound, v16i8:$Src, i32:$PS), - (BCDSR_rec $ShiftRound, $Src, $PS)>; - -def : Pat<(PPCbcdtrunc v4i32:$Trunc, v16i8:$Src, i32:$PS), - (BCDTRUNC_rec $Trunc, $Src, $PS)>; - -def : Pat<(PPCbcdutrunc v4i32:$Trunc, v16i8:$Src), - (BCDUTRUNC_rec $Trunc, $Src)>; - -def : Pat<(PPCbcdus v4i32:$Shift, v16i8:$Src), - (BCDUS_rec $Shift, $Src)>; - def crnot : OutPatFrag<(ops node:$in), (CRNOT $in)>; def : Pat<(not i1:$in), >From 3025959bcf46376e897797351144b1c71080c8e0 Mon Sep 17 00:00:00 2001 From: AditiRM <[email protected]> Date: Mon, 6 Oct 2025 07:28:40 +0000 Subject: [PATCH 13/13] [nit] improve the commit message --- llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index b1cdc0e36ea94..46cba20127580 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -1645,7 +1645,7 @@ def BCDSR_rec : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>; def BCDTRUNC_rec : VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>; def BCDUTRUNC_rec : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>; -// Patterns mapping BCD DAG nodes to machine instructions +// Patterns mapping BCD PPCISD nodes to machine instructions def : Pat<(PPCbcds v4i32:$Shift, v16i8:$Src, i32:$PS), (BCDS_rec $Shift, $Src, $PS)>; _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
