llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-x86 @llvm/pr-subscribers-clang Author: Mikołaj Piróg (mikolaj-pirog) <details> <summary>Changes</summary> Per Intel Architecture Instruction Set Extensions Programming Reference rev. 59 (https://cdrdv2.intel.com/v1/dl/getContent/671368), table 1-2, DMR doesn't support USER_MSR (URDMSR and UWRMSR instructions) --- Full diff: https://github.com/llvm/llvm-project/pull/164232.diff 3 Files Affected: - (modified) clang/test/Preprocessor/predefined-arch-macros.c (-2) - (modified) llvm/lib/Target/X86/X86.td (-1) - (modified) llvm/lib/TargetParser/X86TargetParser.cpp (+1-1) ``````````diff diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c index e2f4bcbfd2382..9f24147f707ce 100644 --- a/clang/test/Preprocessor/predefined-arch-macros.c +++ b/clang/test/Preprocessor/predefined-arch-macros.c @@ -1911,7 +1911,6 @@ // CHECK_GNR_M32: #define __TSXLDTRK__ 1 // CHECK_GNR_M32: #define __UINTR__ 1 // CHECK_GNR_M32-NOT: #define __USERMSR__ 1 -// CHECK_DMR_M32: #define __USERMSR__ 1 // CHECK_GNR_M32: #define __VAES__ 1 // CHECK_GNR_M32: #define __VPCLMULQDQ__ 1 // CHECK_GNR_M32: #define __WAITPKG__ 1 @@ -2018,7 +2017,6 @@ // CHECK_GNR_M64: #define __TSXLDTRK__ 1 // CHECK_GNR_M64: #define __UINTR__ 1 // CHECK_GNR_M64-NOT: #define __USERMSR__ 1 -// CHECK_DMR_M64: #define __USERMSR__ 1 // CHECK_GNR_M64: #define __VAES__ 1 // CHECK_GNR_M64: #define __VPCLMULQDQ__ 1 // CHECK_GNR_M64: #define __WAITPKG__ 1 diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 6db780f91f3b9..74e67caf52b02 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -1164,7 +1164,6 @@ def ProcessorFeatures { FeatureAVXNECONVERT, FeatureAVXVNNIINT8, FeatureAVXVNNIINT16, - FeatureUSERMSR, FeatureSHA512, FeatureSM3, FeatureEGPR, diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp index e382cfe9d14fe..43d3a65e8191d 100644 --- a/llvm/lib/TargetParser/X86TargetParser.cpp +++ b/llvm/lib/TargetParser/X86TargetParser.cpp @@ -144,7 +144,7 @@ constexpr FeatureBitset FeaturesDiamondRapids = FeatureSM4 | FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 | FeaturePPX | FeatureNDD | FeatureNF | FeatureMOVRS | FeatureAMX_MOVRS | FeatureAMX_AVX512 | FeatureAMX_FP8 | FeatureAMX_TF32 | - FeatureAMX_TRANSPOSE | FeatureUSERMSR; + FeatureAMX_TRANSPOSE; // Intel Atom processors. // Bonnell has feature parity with Core2 and adds MOVBE. `````````` </details> https://github.com/llvm/llvm-project/pull/164232 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
