llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-aarch64 Author: None (Red-RobinHood) <details> <summary>Changes</summary> --- Full diff: https://github.com/llvm/llvm-project/pull/167177.diff 2 Files Affected: - (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+32) - (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.h (+7) ``````````diff diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index c8a038fa99b30..7604cdc786268 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -31527,6 +31527,38 @@ bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode( Op, OriginalDemandedBits, OriginalDemandedElts, Known, TLO, Depth); } +bool AArch64TargetLowering::SimplifyDemandedVectorEltsForTargetNode( + SDValue Op, + const APInt &DemandedElts, + APInt &KnownUndef, + APInt &KnownZero, + TargetLoweringOpt &TLO, + unsigned Depth) const { + + SDNode *N = Op.getNode(); + unsigned Opc = N->getOpcode(); + + if (Opc != AArch64ISD::DUPLANE8 && + Opc != AArch64ISD::DUPLANE16 && + Opc != AArch64ISD::DUPLANE32 && + Opc != AArch64ISD::DUPLANE64) + return false; + + if (DemandedElts.popcount() != 1) + return false; + + SDValue Src = N->getOperand(0); + SDValue Lane = N->getOperand(1); + + SDLoc DL(N); + SelectionDAG &DAG = TLO.DAG; + + SDValue Extracted = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Src.getValueType().getScalarType(), Src, Lane); + SDValue Splat = DAG.getSplatVector(Op.getValueType(), DL, Extracted); + + return TLO.CombineTo(Op, Splat); +} + bool AArch64TargetLowering::canCreateUndefOrPoisonForTargetNode( SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const { diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 70bfae717fb76..6cd26fe871a60 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -880,6 +880,13 @@ class AArch64TargetLowering : public TargetLowering { TargetLoweringOpt &TLO, unsigned Depth) const override; + bool SimplifyDemandedVectorEltsForTargetNode(SDValue Op, + const APInt &DemandedElts, + APInt &KnownUndef, + APInt &KnownZero, + TargetLoweringOpt &TLO, + unsigned Depth) const override; + bool canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, `````````` </details> https://github.com/llvm/llvm-project/pull/167177 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
