================
@@ -1556,10 +1556,14 @@ void CIRGenModule::emitTopLevelDecl(Decl *decl) {
break;
case Decl::ClassTemplateSpecialization:
- case Decl::CXXRecord:
+ case Decl::CXXRecord: {
+ CXXRecordDecl *crd = cast<CXXRecordDecl>(decl);
assert(!cir::MissingFeatures::generateDebugInfo());
- assert(!cir::MissingFeatures::cxxRecordStaticMembers());
+ for (auto *childDecl : crd->decls())
+ if (isa<VarDecl>(childDecl) || isa<CXXRecordDecl>(childDecl))
----------------
erichkeane wrote:
```suggestion
if (isa<VarDecl, CXXRecordDecl>(childDecl))
```
https://github.com/llvm/llvm-project/pull/169134
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