https://github.com/andykaylor updated https://github.com/llvm/llvm-project/pull/169134
>From b4d5cbe28641a8e7ed6df79e2a1756b53ff4bb67 Mon Sep 17 00:00:00 2001 From: Andy Kaylor <[email protected]> Date: Fri, 21 Nov 2025 15:19:13 -0800 Subject: [PATCH 1/2] [CIR] Add handling for static data members This adds some trivial handling to force emitting of child decls inside C++ records. --- clang/include/clang/CIR/MissingFeatures.h | 1 - clang/lib/CIR/CodeGen/CIRGenModule.cpp | 8 +++- clang/test/CIR/CodeGen/static-members.cpp | 53 +++++++++++++++++++++++ 3 files changed, 59 insertions(+), 3 deletions(-) create mode 100644 clang/test/CIR/CodeGen/static-members.cpp diff --git a/clang/include/clang/CIR/MissingFeatures.h b/clang/include/clang/CIR/MissingFeatures.h index 2ecde9aa5d56d..960740eeda36c 100644 --- a/clang/include/clang/CIR/MissingFeatures.h +++ b/clang/include/clang/CIR/MissingFeatures.h @@ -239,7 +239,6 @@ struct MissingFeatures { static bool ctorConstLvalueToRvalueConversion() { return false; } static bool ctorMemcpyizer() { return false; } static bool cudaSupport() { return false; } - static bool cxxRecordStaticMembers() { return false; } static bool dataLayoutTypeIsSized() { return false; } static bool dataLayoutTypeAllocSize() { return false; } static bool dataLayoutTypeStoreSize() { return false; } diff --git a/clang/lib/CIR/CodeGen/CIRGenModule.cpp b/clang/lib/CIR/CodeGen/CIRGenModule.cpp index e09d3de5aac9a..9efeb3ab11375 100644 --- a/clang/lib/CIR/CodeGen/CIRGenModule.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenModule.cpp @@ -1556,10 +1556,14 @@ void CIRGenModule::emitTopLevelDecl(Decl *decl) { break; case Decl::ClassTemplateSpecialization: - case Decl::CXXRecord: + case Decl::CXXRecord: { + CXXRecordDecl *crd = cast<CXXRecordDecl>(decl); assert(!cir::MissingFeatures::generateDebugInfo()); - assert(!cir::MissingFeatures::cxxRecordStaticMembers()); + for (auto *childDecl : crd->decls()) + if (isa<VarDecl>(childDecl) || isa<CXXRecordDecl>(childDecl)) + emitTopLevelDecl(childDecl); break; + } case Decl::FileScopeAsm: // File-scope asm is ignored during device-side CUDA compilation. diff --git a/clang/test/CIR/CodeGen/static-members.cpp b/clang/test/CIR/CodeGen/static-members.cpp new file mode 100644 index 0000000000000..2ffc1aaf3f197 --- /dev/null +++ b/clang/test/CIR/CodeGen/static-members.cpp @@ -0,0 +1,53 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir +// RUN: FileCheck %s -check-prefix=CIR --input-file=%t.cir +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t-cir.ll +// RUN: FileCheck %s -check-prefix=LLVM --input-file=%t-cir.ll +// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o %t.ll +// RUN: FileCheck %s -check-prefix=OGCG --input-file=%t.ll + +struct HasDtor { + ~HasDtor(); +}; +struct S { + static inline HasDtor hd; +}; + +// CIR: cir.global linkonce_odr comdat @_ZN1S2hdE = #cir.zero : !rec_HasDtor + +// CIR: cir.func internal private @__cxx_global_var_init() { +// CIR: %[[HD:.*]] = cir.get_global @_ZN1S2hdE : !cir.ptr<!rec_HasDtor> +// CIR: %[[DTOR:.*]] = cir.get_global @_ZN7HasDtorD1Ev : !cir.ptr<!cir.func<(!cir.ptr<!rec_HasDtor>)>> +// CIR: %[[DTOR_CAST:.*]] = cir.cast bitcast %[[DTOR]] : !cir.ptr<!cir.func<(!cir.ptr<!rec_HasDtor>)>> -> !cir.ptr<!cir.func<(!cir.ptr<!void>)>> +// CIR: %[[HD_CAST:.*]] = cir.cast bitcast %[[HD]] : !cir.ptr<!rec_HasDtor> -> !cir.ptr<!void> +// CIR: %[[HANDLE:.*]] = cir.get_global @__dso_handle : !cir.ptr<i8> +// CIR: cir.call @__cxa_atexit(%[[DTOR_CAST]], %[[HD_CAST]], %[[HANDLE]]) + +// CIR: cir.func private @_GLOBAL__sub_I_static_members.cpp() +// CIR: cir.call @__cxx_global_var_init() + +// LLVM: @_ZN1S2hdE = linkonce_odr global %struct.HasDtor zeroinitializer, comdat +// LLVM: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_static_members.cpp, ptr null }] +// LLVM: define internal void @__cxx_global_var_init() +// LLVM: call void @__cxa_atexit(ptr @_ZN7HasDtorD1Ev, ptr @_ZN1S2hdE, ptr @__dso_handle) +// LLVM: define void @_GLOBAL__sub_I_static_members.cpp() +// LLVM: call void @__cxx_global_var_init() + +// FIXME(cir): OGCG has a guard variable for this case that we don't generate in CIR. +// This is needed because the variable linkonce_odr linkage. + +// OGCG: @_ZN1S2hdE = linkonce_odr global %struct.HasDtor zeroinitializer, comdat +// OGCG: @_ZGVN1S2hdE = linkonce_odr global i64 0, comdat($_ZN1S2hdE) +// OGCG: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @__cxx_global_var_init, ptr @_ZN1S2hdE }] +// OGCG: define internal void @__cxx_global_var_init() {{.*}} section ".text.startup" comdat($_ZN1S2hdE) { +// OGCG: %[[GUARD:.*]] = load atomic i8, ptr @_ZGVN1S2hdE acquire +// OGCG: %[[UNINIT:.*]] = icmp eq i8 %[[GUARD]], 0 +// OGCG: br i1 %[[UNINIT]], label %[[INIT_CHECK:.*]], label %[[INIT_END:.*]] +// OGCG: [[INIT_CHECK:.*]]: +// OGCG: %[[GUARD_ACQUIRE:.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVN1S2hdE) +// OGCG: %[[TOBOOL:.*]] = icmp ne i32 %[[GUARD_ACQUIRE]], 0 +// OGCG: br i1 %[[TOBOOL]], label %[[INIT:.*]], label %[[INIT_END]] +// OGCG: [[INIT:.*]]: +// OGCG: %[[ATEXIT:.*]] = call i32 @__cxa_atexit(ptr @_ZN7HasDtorD1Ev, ptr @_ZN1S2hdE, ptr @__dso_handle) +// OGCG: call void @__cxa_guard_release(ptr @_ZGVN1S2hdE) +// OGCG: br label %[[INIT_END]] +// OGCG: [[INIT_END]]: >From e7df71729d9644d3f7d7d8b25b2a59beb70ae1de Mon Sep 17 00:00:00 2001 From: Andy Kaylor <[email protected]> Date: Fri, 21 Nov 2025 17:05:58 -0800 Subject: [PATCH 2/2] Address review feedback --- clang/lib/CIR/CodeGen/CIRGenModule.cpp | 2 +- clang/test/CIR/CodeGen/static-members.cpp | 53 ++++++++++++++++++++--- 2 files changed, 48 insertions(+), 7 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenModule.cpp b/clang/lib/CIR/CodeGen/CIRGenModule.cpp index 9efeb3ab11375..251c99c8cd45b 100644 --- a/clang/lib/CIR/CodeGen/CIRGenModule.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenModule.cpp @@ -1560,7 +1560,7 @@ void CIRGenModule::emitTopLevelDecl(Decl *decl) { CXXRecordDecl *crd = cast<CXXRecordDecl>(decl); assert(!cir::MissingFeatures::generateDebugInfo()); for (auto *childDecl : crd->decls()) - if (isa<VarDecl>(childDecl) || isa<CXXRecordDecl>(childDecl)) + if (isa<VarDecl, CXXRecordDecl, EnumDecl>(childDecl)) emitTopLevelDecl(childDecl); break; } diff --git a/clang/test/CIR/CodeGen/static-members.cpp b/clang/test/CIR/CodeGen/static-members.cpp index 2ffc1aaf3f197..8722dc2a2bc6f 100644 --- a/clang/test/CIR/CodeGen/static-members.cpp +++ b/clang/test/CIR/CodeGen/static-members.cpp @@ -22,22 +22,24 @@ struct S { // CIR: %[[HANDLE:.*]] = cir.get_global @__dso_handle : !cir.ptr<i8> // CIR: cir.call @__cxa_atexit(%[[DTOR_CAST]], %[[HD_CAST]], %[[HANDLE]]) -// CIR: cir.func private @_GLOBAL__sub_I_static_members.cpp() -// CIR: cir.call @__cxx_global_var_init() - // LLVM: @_ZN1S2hdE = linkonce_odr global %struct.HasDtor zeroinitializer, comdat +// LLVM: @_ZN5Outer5Inner2hdE = linkonce_odr global %struct.HasDtor zeroinitializer, comdat + // LLVM: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_static_members.cpp, ptr null }] // LLVM: define internal void @__cxx_global_var_init() // LLVM: call void @__cxa_atexit(ptr @_ZN7HasDtorD1Ev, ptr @_ZN1S2hdE, ptr @__dso_handle) -// LLVM: define void @_GLOBAL__sub_I_static_members.cpp() -// LLVM: call void @__cxx_global_var_init() // FIXME(cir): OGCG has a guard variable for this case that we don't generate in CIR. // This is needed because the variable linkonce_odr linkage. // OGCG: @_ZN1S2hdE = linkonce_odr global %struct.HasDtor zeroinitializer, comdat // OGCG: @_ZGVN1S2hdE = linkonce_odr global i64 0, comdat($_ZN1S2hdE) -// OGCG: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @__cxx_global_var_init, ptr @_ZN1S2hdE }] +// OGCG: @_ZN5Outer5Inner2hdE = linkonce_odr global %struct.HasDtor zeroinitializer, comdat +// OGCG: @_ZGVN5Outer5Inner2hdE = linkonce_odr global i64 0, comdat($_ZN5Outer5Inner2hdE) +// OGCG: @llvm.global_ctors = appending global [2 x { i32, ptr, ptr }] [ +// OGCG-SAME: { i32, ptr, ptr } { i32 65535, ptr @__cxx_global_var_init, ptr @_ZN1S2hdE }, +// OGCG-SAME: { i32, ptr, ptr } { i32 65535, ptr @__cxx_global_var_init.1, ptr @_ZN5Outer5Inner2hdE }] + // OGCG: define internal void @__cxx_global_var_init() {{.*}} section ".text.startup" comdat($_ZN1S2hdE) { // OGCG: %[[GUARD:.*]] = load atomic i8, ptr @_ZGVN1S2hdE acquire // OGCG: %[[UNINIT:.*]] = icmp eq i8 %[[GUARD]], 0 @@ -51,3 +53,42 @@ struct S { // OGCG: call void @__cxa_guard_release(ptr @_ZGVN1S2hdE) // OGCG: br label %[[INIT_END]] // OGCG: [[INIT_END]]: + +struct Outer { + struct Inner { + static inline HasDtor hd; + }; +}; + +// CIR: cir.global linkonce_odr comdat @_ZN5Outer5Inner2hdE = #cir.zero : !rec_HasDtor +// CIR: cir.func internal private @__cxx_global_var_init.1() +// CIR: %[[HD:.*]] = cir.get_global @_ZN5Outer5Inner2hdE : !cir.ptr<!rec_HasDtor> +// CIR: %[[DTOR:.*]] = cir.get_global @_ZN7HasDtorD1Ev : !cir.ptr<!cir.func<(!cir.ptr<!rec_HasDtor>)>> +// CIR: %[[DTOR_CAST:.*]] = cir.cast bitcast %[[DTOR]] : !cir.ptr<!cir.func<(!cir.ptr<!rec_HasDtor>)>> -> !cir.ptr<!cir.func<(!cir.ptr<!void>)>> +// CIR: %[[HD_CAST:.*]] = cir.cast bitcast %[[HD]] : !cir.ptr<!rec_HasDtor> -> !cir.ptr<!void> +// CIR: %[[HANDLE:.*]] = cir.get_global @__dso_handle : !cir.ptr<i8> +// CIR: cir.call @__cxa_atexit(%[[DTOR_CAST]], %[[HD_CAST]], %[[HANDLE]]) : (!cir.ptr<!cir.func<(!cir.ptr<!void>)>>, !cir.ptr<!void>, !cir.ptr<i8>) -> () + +// LLVM: define internal void @__cxx_global_var_init.1() +// LLVM: call void @__cxa_atexit(ptr @_ZN7HasDtorD1Ev, ptr @_ZN5Outer5Inner2hdE, ptr @__dso_handle) + +// OGCG: define internal void @__cxx_global_var_init.1() {{.*}} section ".text.startup" comdat($_ZN5Outer5Inner2hdE) { +// OGCG: %[[GUARD:.*]] = load atomic i8, ptr @_ZGVN5Outer5Inner2hdE acquire +// OGCG: %[[UNINIT:.*]] = icmp eq i8 %[[GUARD]], 0 +// OGCG: br i1 %[[UNINIT]], label %[[INIT_CHECK:.*]], label %[[INIT_END:.*]] +// OGCG: [[INIT_CHECK:.*]]: +// OGCG: %[[GUARD_ACQUIRE:.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVN5Outer5Inner2hdE) +// OGCG: %[[TOBOOL:.*]] = icmp ne i32 %[[GUARD_ACQUIRE]], 0 +// OGCG: br i1 %[[TOBOOL]], label %[[INIT:.*]], label %[[INIT_END]] +// OGCG: [[INIT:.*]]: +// OGCG: %[[ATEXIT:.*]] = call i32 @__cxa_atexit(ptr @_ZN7HasDtorD1Ev, ptr @_ZN5Outer5Inner2hdE, ptr @__dso_handle) +// OGCG: call void @__cxa_guard_release(ptr @_ZGVN5Outer5Inner2hdE) +// OGCG: br label %[[INIT_END]] +// OGCG: [[INIT_END]]: + + +// CIR: cir.func private @_GLOBAL__sub_I_static_members.cpp() +// CIR: cir.call @__cxx_global_var_init() + +// LLVM: define void @_GLOBAL__sub_I_static_members.cpp() +// LLVM: call void @__cxx_global_var_init() _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
