llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-aarch64 Author: None (CarolineConcatto) <details> <summary>Changes</summary> This patch add supports in Clang for these assembly intrinsics: FRINT32X FRINT32Z FRINT64X FRINT64Z By adding support for these intrinsics: // Variant is available for _f64 svfloat32_t svrint32x[_f32]_z(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32x[_f32]_x(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32x[_f32]_m(svfloat32_t inactive, svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32z[_f32]_z(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32z[_f32]_x(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint32z[_f32]_m(svfloat32_t inactive, svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64x[_f32]_z(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64x[_f32]_x(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64x[_f32]_m(svfloat32_t inactive, svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64z[_f32]_z(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64z[_f32]_x(svbool_t pg, svfloat32_t zn); // Variant is available for _f64 svfloat32_t svrint64z[_f32]_m(svfloat32_t inactive, svbool_t pg, svfloat32_t zn); ``` according to the ACLE[1] [1]https://github.com/ARM-software/acle/pull/412 --- Patch is 52.23 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/169661.diff 7 Files Affected: - (modified) clang/include/clang/Basic/arm_sve.td (+7) - (added) clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c (+445) - (modified) llvm/include/llvm/IR/IntrinsicsAArch64.td (+4) - (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+17) - (modified) llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (+12-8) - (modified) llvm/lib/Target/AArch64/SVEInstrFormats.td (+17-2) - (added) llvm/test/CodeGen/AArch64/sve2p2-intrinsics-fp-arith.ll (+283) ``````````diff diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index d2b7b78b9970f..070c2b9509de8 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -778,6 +778,13 @@ defm SVRINTX : SInstZPZ<"svrintx", "hfd", "aarch64_sve_frintx">; defm SVRINTZ : SInstZPZ<"svrintz", "hfd", "aarch64_sve_frintz">; defm SVSQRT : SInstZPZ<"svsqrt", "hfd", "aarch64_sve_fsqrt">; +let SVETargetGuard = "sve2p2|sme2p2", SMETargetGuard = "sve2p2|sme2p2" in { +defm SVRINT32X : SInstZPZ<"svrint32x", "fd", "aarch64_sve_frint32x">; +defm SVRINT32Z : SInstZPZ<"svrint32z", "fd", "aarch64_sve_frint32z">; +defm SVRINT64X : SInstZPZ<"svrint64x", "fd", "aarch64_sve_frint64x">; +defm SVRINT64Z : SInstZPZ<"svrint64z", "fd", "aarch64_sve_frint64z">; +} + let SMETargetGuard = "sme2,ssve-fexpa" in { def SVEXPA : SInst<"svexpa[_{d}]", "du", "hfd", MergeNone, "aarch64_sve_fexpa_x", [VerifyRuntimeMode]>; } diff --git a/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c b/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c new file mode 100644 index 0000000000000..2b275210e9446 --- /dev/null +++ b/clang/test/CodeGen/AArch64/sve2p2-intrinsics/acle_sve_rintx.c @@ -0,0 +1,445 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: aarch64-registered-target +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 \ +// RUN: -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sme2 -target-feature +sme2p2 \ +// RUN: -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme -target-feature +sve2p2 \ +// RUN: -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme -target-feature +sme2p2 \ +// RUN: -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 \ +// RUN: -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 \ +// RUN: -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 \ +// RUN: -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sve2 -target-feature +sve2p2 \ +// RUN: -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// +#include <arm_sve.h> + +#if defined __ARM_FEATURE_SME +#define MODE_ATTR __arm_streaming +#else +#define MODE_ATTR +#endif + +#ifdef SVE_OVERLOADED_FORMS +// A simple used,unused... macro, long enough to represent any SVE builtin. +#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3 +#else +#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4 +#endif + +// FRINT32X +// CHECK-LABEL: @test_svrint32x_f32_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint32x_f32_mu13__SVFloat32_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +svfloat32_t test_svrint32x_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint32x,_f32,_m,)(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrint32x_f64_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint32x_f64_mu13__SVFloat64_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +svfloat64_t test_svrint32x_f64_m(svfloat64_t inactive, svbool_t pg, svfloat64_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint32x,_f64,_m,)(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrint32x_f32_x( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint32x_f32_xu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +svfloat32_t test_svrint32x_f32_x(svbool_t pg, svfloat32_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint32x,_f32,_x,)(pg, op); +} + +// CHECK-LABEL: @test_svrint32x_f64_x( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint32x_f64_xu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +svfloat64_t test_svrint32x_f64_x(svbool_t pg, svfloat64_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint32x,_f64,_x,)(pg, op); +} + +// CHECK-LABEL: @test_svrint32x_f32_z( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint32x_f32_zu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint32x.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +svfloat32_t test_svrint32x_f32_z(svbool_t pg, svfloat32_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint32x,_f32,_z,)(pg, op); +} + +// CHECK-LABEL: @test_svrint32x_f64_z( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint32x_f64_zu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint32x.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +svfloat64_t test_svrint32x_f64_z(svbool_t pg, svfloat64_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint32x,_f64,_z,)(pg, op); +} + +// FRINT32Z +// CHECK-LABEL: @test_svrint32z_f32_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint32z_f32_mu13__SVFloat32_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +svfloat32_t test_svrint32z_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint32z,_f32,_m,)(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrint32z_f64_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint32z_f64_mu13__SVFloat64_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +svfloat64_t test_svrint32z_f64_m(svfloat64_t inactive, svbool_t pg, svfloat64_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint32z,_f64,_m,)(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrint32z_f32_x( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint32z_f32_xu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +svfloat32_t test_svrint32z_f32_x(svbool_t pg, svfloat32_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint32z,_f32,_x,)(pg, op); +} + +// CHECK-LABEL: @test_svrint32z_f64_x( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint32z_f64_xu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> undef, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +svfloat64_t test_svrint32z_f64_x(svbool_t pg, svfloat64_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint32z,_f64,_x,)(pg, op); +} + +// CHECK-LABEL: @test_svrint32z_f32_z( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint32z_f32_zu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint32z.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +svfloat32_t test_svrint32z_f32_z(svbool_t pg, svfloat32_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint32z,_f32,_z,)(pg, op); +} + +// CHECK-LABEL: @test_svrint32z_f64_z( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint32z_f64_zu10__SVBool_tu13__SVFloat64_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint32z.nxv2f64(<vscale x 2 x double> zeroinitializer, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +svfloat64_t test_svrint32z_f64_z(svbool_t pg, svfloat64_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint32z,_f64,_z,)(pg, op); +} + +// FRINT64X +// CHECK-LABEL: @test_svrint64x_f32_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint64x.nxv4f32(<vscale x 4 x float> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint64x_f32_mu13__SVFloat32_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint64x.nxv4f32(<vscale x 4 x float> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +svfloat32_t test_svrint64x_f32_m(svfloat32_t inactive, svbool_t pg, svfloat32_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint64x,_f32,_m,)(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrint64x_f64_m( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint64x.nxv2f64(<vscale x 2 x double> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint64x_f64_mu13__SVFloat64_tu10__SVBool_tS_( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.frint64x.nxv2f64(<vscale x 2 x double> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]] +// +svfloat64_t test_svrint64x_f64_m(svfloat64_t inactive, svbool_t pg, svfloat64_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint64x,_f64,_m,)(inactive, pg, op); +} + +// CHECK-LABEL: @test_svrint64x_f32_x( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint64x.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +// CPP-CHECK-LABEL: @_Z20test_svrint64x_f32_xu10__SVBool_tu13__SVFloat32_t( +// CPP-CHECK-NEXT: entry: +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.frint64x.nxv4f32(<vscale x 4 x float> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP:%.*]]) +// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]] +// +svfloat32_t test_svrint64x_f32_x(svbool_t pg, svfloat32_t op) MODE_ATTR +{ + return SVE_ACLE_FUNC(svrint64x,_f32,_x,)(pg, op); +} + +// CHECK-LABEL: @test_svrint64x_f... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/169661 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
