https://github.com/moar55 updated https://github.com/llvm/llvm-project/pull/169566
>From 885eaa5d8a9a33e333c521e78b5a4fdcf3bd14b9 Mon Sep 17 00:00:00 2001 From: Omar Ibrahim <[email protected]> Date: Thu, 20 Nov 2025 23:12:40 +0100 Subject: [PATCH 1/5] [CIR] Implement x86 rotate builtins --- clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 42 +++++++++ .../CodeGenBuiltins/X86/avx512f-builtins.c | 51 ++++++++-- .../CIR/CodeGenBuiltins/X86/xop-builtins.c | 92 +++++++++++++++++++ shell.nix | 14 +++ 4 files changed, 190 insertions(+), 9 deletions(-) create mode 100644 clang/test/CIR/CodeGenBuiltins/X86/xop-builtins.c create mode 100644 shell.nix diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index b242efc00e491..8ebabf704bc80 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -11,10 +11,14 @@ // //===----------------------------------------------------------------------===// +#include "CIRGenBuilder.h" #include "CIRGenFunction.h" #include "CIRGenModule.h" +#include "mlir/IR/Location.h" +#include "mlir/IR/ValueRange.h" #include "clang/Basic/Builtins.h" #include "clang/Basic/TargetBuiltins.h" +#include "clang/CIR/Dialect/IR/CIRTypes.h" #include "clang/CIR/MissingFeatures.h" using namespace clang; @@ -115,6 +119,40 @@ static mlir::Value emitX86MaskLogic(CIRGenBuilderTy &builder, ops[0].getType()); } +static mlir::Value emitX86FunnelShift(CIRGenBuilderTy &builder, + mlir::Location location, mlir::Value &op0, + mlir::Value &op1, mlir::Value &amt, + bool isRight) { + mlir::Type op0Ty = op0.getType(); + + // Amount may be scalar immediate, in which case create a splat vector. + // Funnel shifts amounts are treated as modulo and types are all power-of-2 + // so we only care about the lowest log2 bits anyway. + if (amt.getType() != op0Ty) { + auto vecTy = mlir::cast<cir::VectorType>(op0Ty); + uint64_t numElems = vecTy.getSize(); + + auto amtTy = mlir::cast<cir::IntType>(amt.getType()); + auto vecElemTy = mlir::cast<cir::IntType>(vecTy.getElementType()); + + // Cast to same width unsigned if not already unsigned. + if (amtTy.isSigned()) { + cir::IntType unsignedAmtTy = builder.getUIntNTy(amtTy.getWidth()); + amt = builder.createIntCast(amt, unsignedAmtTy); + } + // Cast the unsigned `amt` to operand element type's width unsigned. + cir::IntType unsignedVecElemType = builder.getUIntNTy(vecElemTy.getWidth()); + amt = builder.createIntCast(amt, unsignedVecElemType); + amt = cir::VecSplatOp::create( + builder, location, cir::VectorType::get(unsignedVecElemType, numElems), + amt); + } + + const StringRef intrinsicName = isRight ? "fshr" : "fshl"; + return emitIntrinsicCallOp(builder, location, intrinsicName, op0Ty, + mlir::ValueRange{op0, op1, amt}); +} + mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) { if (builtinID == Builtin::BI__builtin_cpu_is) { @@ -691,12 +729,16 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, case X86::BI__builtin_ia32_prolq128: case X86::BI__builtin_ia32_prolq256: case X86::BI__builtin_ia32_prolq512: + return emitX86FunnelShift(this->getBuilder(), getLoc(expr->getExprLoc()), + ops[0], ops[0], ops[1], false); case X86::BI__builtin_ia32_prord128: case X86::BI__builtin_ia32_prord256: case X86::BI__builtin_ia32_prord512: case X86::BI__builtin_ia32_prorq128: case X86::BI__builtin_ia32_prorq256: case X86::BI__builtin_ia32_prorq512: + return emitX86FunnelShift(this->getBuilder(), getLoc(expr->getExprLoc()), + ops[0], ops[0], ops[1], true); case X86::BI__builtin_ia32_selectb_128: case X86::BI__builtin_ia32_selectb_256: case X86::BI__builtin_ia32_selectb_512: diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c index 31d6bc3d22408..99068b7df6e40 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c @@ -18,12 +18,12 @@ __m512 test_mm512_undefined(void) { // CIR-LABEL: _mm512_undefined // CIR: %[[A:.*]] = cir.const #cir.zero : !cir.vector<8 x !cir.double> - // CIR: %{{.*}} = cir.cast bitcast %[[A]] : !cir.vector<8 x !cir.double> -> !cir.vector<16 x !cir.float> + // CIR: cir.cast bitcast %[[A]] : !cir.vector<8 x !cir.double> -> !cir.vector<16 x !cir.float> // CIR: cir.return %{{.*}} : !cir.vector<16 x !cir.float> // LLVM-LABEL: test_mm512_undefined // LLVM: store <16 x float> zeroinitializer, ptr %[[A:.*]], align 64 - // LLVM: %{{.*}} = load <16 x float>, ptr %[[A]], align 64 + // LLVM: load <16 x float>, ptr %[[A]], align 64 // LLVM: ret <16 x float> %{{.*}} // OGCG-LABEL: test_mm512_undefined @@ -34,12 +34,12 @@ __m512 test_mm512_undefined(void) { __m512 test_mm512_undefined_ps(void) { // CIR-LABEL: _mm512_undefined_ps // CIR: %[[A:.*]] = cir.const #cir.zero : !cir.vector<8 x !cir.double> - // CIR: %{{.*}} = cir.cast bitcast %[[A]] : !cir.vector<8 x !cir.double> -> !cir.vector<16 x !cir.float> + // CIR: cir.cast bitcast %[[A]] : !cir.vector<8 x !cir.double> -> !cir.vector<16 x !cir.float> // CIR: cir.return %{{.*}} : !cir.vector<16 x !cir.float> // LLVM-LABEL: test_mm512_undefined_ps // LLVM: store <16 x float> zeroinitializer, ptr %[[A:.*]], align 64 - // LLVM: %{{.*}} = load <16 x float>, ptr %[[A]], align 64 + // LLVM: load <16 x float>, ptr %[[A]], align 64 // LLVM: ret <16 x float> %{{.*}} // OGCG-LABEL: test_mm512_undefined_ps @@ -49,12 +49,12 @@ __m512 test_mm512_undefined_ps(void) { __m512d test_mm512_undefined_pd(void) { // CIR-LABEL: _mm512_undefined_pd - // CIR: %{{.*}} = cir.const #cir.zero : !cir.vector<8 x !cir.double> + // CIR: cir.const #cir.zero : !cir.vector<8 x !cir.double> // CIR: cir.return %{{.*}} : !cir.vector<8 x !cir.double> // LLVM-LABEL: test_mm512_undefined_pd // LLVM: store <8 x double> zeroinitializer, ptr %[[A:.*]], align 64 - // LLVM: %{{.*}} = load <8 x double>, ptr %[[A]], align 64 + // LLVM: load <8 x double>, ptr %[[A]], align 64 // LLVM: ret <8 x double> %{{.*}} // OGCG-LABEL: test_mm512_undefined_pd @@ -64,13 +64,13 @@ __m512d test_mm512_undefined_pd(void) { __m512i test_mm512_undefined_epi32(void) { // CIR-LABEL: _mm512_undefined_epi32 - // CIR: %[[A:.*]] = cir.const #cir.zero : !cir.vector<8 x !cir.double> - // CIR: %{{.*}} = cir.cast bitcast %[[A]] : !cir.vector<8 x !cir.double> -> !cir.vector<8 x !s64i> + // CIR: cir.const #cir.zero : !cir.vector<8 x !cir.double> + // CIR: cir.cast bitcast %[[A]] : !cir.vector<8 x !cir.double> -> !cir.vector<8 x !s64i> // CIR: cir.return %{{.*}} : !cir.vector<8 x !s64i> // LLVM-LABEL: test_mm512_undefined_epi32 // LLVM: store <8 x i64> zeroinitializer, ptr %[[A:.*]], align 64 - // LLVM: %{{.*}} = load <8 x i64>, ptr %[[A]], align 64 + // LLVM: load <8 x i64>, ptr %[[A]], align 64 // LLVM: ret <8 x i64> %{{.*}} // OGCG-LABEL: test_mm512_undefined_epi32 @@ -228,3 +228,36 @@ __mmask16 test_kmov_w(__mmask16 A) { // OGCG: bitcast <16 x i1> {{.*}} to i16 return __builtin_ia32_kmovw(A); } + +__m512i test_mm512_ror_epi32(__m512i __A) { + // CIR-LABEL: test_mm512_ror_epi32 + // CIR: cir.cast integral %{{.*}} : !s32i -> !u32i + // CIR: cir.vec.splat %{{.*}} : !u32i, !cir.vector<16 x !u32i> + // CIR: cir.call_llvm_intrinsic "fshr" {{%.*}}: (!cir.vector<16 x !s32i>, !cir.vector<16 x !s32i>, !cir.vector<16 x !u32i>) -> !cir.vector<16 x !s32i> + + // LLVM-LABEL: test_mm512_ror_epi32 + // LLVM: %[[CASTED_VAR:.*]] = bitcast <8 x i64> %{{.*}} to <16 x i32> + // LLVM: call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %[[CASTED_VAR]], <16 x i32> %[[CASTED_VAR]], <16 x i32> splat (i32 5)) + + // OGCG-LABEL: test_mm512_ror_epi32 + // OGCG: %[[CASTED_VAR:.*]] = bitcast <8 x i64> %{{.*}} to <16 x i32> + // OGCG: call <16 x i32> @llvm.fshr.v16i32(<16 x i32> %[[CASTED_VAR]], <16 x i32> %[[CASTED_VAR]], <16 x i32> splat (i32 5)) + return _mm512_ror_epi32(__A, 5); +} + +__m512i test_mm512_ror_epi64(__m512i __A) { + // CIR-LABEL: test_mm512_ror_epi64 + // CIR: cir.cast integral %{{.*}} : !s32i -> !u32i + // CIR: cir.cast integral %{{.*}} : !u32i -> !u64i + // CIR: cir.vec.splat %{{.*}} : !u64i, !cir.vector<8 x !u64i> + // CIR: cir.call_llvm_intrinsic "fshr" {{%.*}}: (!cir.vector<8 x !s64i>, !cir.vector<8 x !s64i>, !cir.vector<8 x !u64i>) -> !cir.vector<8 x !s64i> + + // LLVM-LABEL: test_mm512_ror_epi64 + // LLVM: %[[VAR:.*]] = load <8 x i64>, ptr {{%.*}}, align 64 + // LLVM: call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %[[VAR]], <8 x i64> %[[VAR]], <8 x i64> splat (i64 5)) + + // OGCG-LABEL: test_mm512_ror_epi64 + // OGCG: %[[VAR:.*]] = load <8 x i64>, ptr {{%.*}}, align 64 + // OGCG: call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %[[VAR]], <8 x i64> %[[VAR]], <8 x i64> splat (i64 5)) + return _mm512_ror_epi64(__A, 5); +} diff --git a/clang/test/CIR/CodeGenBuiltins/X86/xop-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/xop-builtins.c new file mode 100644 index 0000000000000..c10fc1ca486df --- /dev/null +++ b/clang/test/CIR/CodeGenBuiltins/X86/xop-builtins.c @@ -0,0 +1,92 @@ +// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +xop -emit-cir -o %t.cir +// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s +// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +xop -fno-signed-char -emit-cir -o %t.cir +// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s + +// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +xop -fclangir -emit-llvm -o %t.ll +// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s +// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +xop -fno-signed-char -fclangir -emit-llvm -o %t.ll +// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s + +// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +xop -emit-cir -o %t.cir +// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s +// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +xop -fno-signed-char -emit-cir -o %t.cir +// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s + +// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +xop -fclangir -emit-llvm -o %t.ll +// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s +// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +xop -fno-signed-char -fclangir -emit-llvm -o %t.ll +// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s + +// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +xop -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=OGCG +// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +xop -fno-signed-char -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=OGCG +// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +xop -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=OGCG +// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +xop -fno-signed-char -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=OGCG + +#include <x86intrin.h> + +// This test mimics clang/test/CodeGen/X86/xop-builtins.c, which eventually +// CIR shall be able to support fully. + +__m128i test_mm_roti_epi8(__m128i a) { + // CIR-LABEL: test_mm_roti_epi8 + // CIR: cir.vec.splat %{{.*}} : !{{[us]}}8i, !cir.vector<16 x !{{[us]}}8i> + // CIR: cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<16 x !{{[su]}}8i>, !cir.vector<16 x !{{[su]}}8i>, !cir.vector<16 x !{{[su]}}8i>) -> !cir.vector<16 x !{{[su]}}8i> + + // LLVM-LABEL: test_mm_roti_epi8 + // LLVM: %[[CASTED_VAR:.*]] = bitcast <2 x i64> %{{.*}} to <16 x i8> + // LLVM: call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %[[CASTED_VAR]], <16 x i8> %[[CASTED_VAR]], <16 x i8> splat (i8 1)) + + // OGCG-LABEL: test_mm_roti_epi8 + // OGCG: %[[CASTED_VAR:.*]] = bitcast <2 x i64> %{{.*}} to <16 x i8> + // OGCG: call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %[[CASTED_VAR]], <16 x i8> %[[CASTED_VAR]], <16 x i8> splat (i8 1)) + return _mm_roti_epi8(a, 1); +} + +__m128i test_mm_roti_epi16(__m128i a) { + // CIR-LABEL: test_mm_roti_epi16 + // CIR: cir.cast integral %{{.*}} : !u8i -> !u16i + // CIR: cir.vec.splat %{{.*}} : !{{[us]}}16i, !cir.vector<8 x !u16i> + // CIR: cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<8 x !{{[su]}}16i>, !cir.vector<8 x !{{[su]}}16i>, !cir.vector<8 x !u16i>) -> !cir.vector<8 x !{{[su]}}16i> + + // LLVM-LABEL: test_mm_roti_epi16 + // LLVM: %[[CASTED_VAR:.*]] = bitcast <2 x i64> %{{.*}} to <8 x i16> + // LLVM: call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %[[CASTED_VAR]], <8 x i16> %[[CASTED_VAR]], <8 x i16> splat (i16 50)) + + // OGCG-LABEL: test_mm_roti_epi16 + // OGCG: %[[CASTED_VAR:.*]] = bitcast <2 x i64> %{{.*}} to <8 x i16> + // OGCG: call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %[[CASTED_VAR]], <8 x i16> %[[CASTED_VAR]], <8 x i16> splat (i16 50)) + return _mm_roti_epi16(a, 50); + } + +__m128i test_mm_roti_epi32(__m128i a) { + // CIR-LABEL: test_mm_roti_epi32 + // CIR: cir.cast integral %{{.*}} : !u8i -> !u32i + // CIR: cir.vec.splat %{{.*}} : !{{[us]}}32i, !cir.vector<4 x !u32i> + // CIR: cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<4 x !{{[su]}}32i>, !cir.vector<4 x !{{[su]}}32i>, !cir.vector<4 x !u32i>) -> !cir.vector<4 x !{{[su]}}32i> + + // LLVM-LABEL: test_mm_roti_epi32 + // LLVM: %[[CASTED_VAR:.*]] = bitcast <2 x i64> %{{.*}} to <4 x i32> + // LLVM: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %[[CASTED_VAR]], <4 x i32> %[[CASTED_VAR]], <4 x i32> splat (i32 226)) + + // OGCG-LABEL: test_mm_roti_epi32 + // OGCG: %[[CASTED_VAR:.*]] = bitcast <2 x i64> %{{.*}} to <4 x i32> + // OGCG: call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %[[CASTED_VAR]], <4 x i32> %[[CASTED_VAR]], <4 x i32> splat (i32 226)) + return _mm_roti_epi32(a, -30); + } + +__m128i test_mm_roti_epi64(__m128i a) { + // CIR-LABEL: test_mm_roti_epi64 + // CIR: cir.cast integral %{{.*}} : !u8i -> !u64i + // CIR: cir.vec.splat %{{.*}} : !u64i, !cir.vector<2 x !u64i> + // CIR: cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<2 x !{{[su]}}64i>, !cir.vector<2 x !{{[su]}}64i>, !cir.vector<2 x !u64i>) -> !cir.vector<2 x !s64i> + + // LLVM-LABEL: test_mm_roti_epi64 + // LLVM: %[[VAR:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 + // LLVM: call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %[[VAR]], <2 x i64> %[[VAR]], <2 x i64> splat (i64 100)) + + // OGCG-LABEL: test_mm_roti_epi64 + // OGCG: %[[VAR:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 + // OGCG: call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %[[VAR]], <2 x i64> %[[VAR]], <2 x i64> splat (i64 100)) + return _mm_roti_epi64(a, 100); + } diff --git a/shell.nix b/shell.nix new file mode 100644 index 0000000000000..c30f6dc7b6928 --- /dev/null +++ b/shell.nix @@ -0,0 +1,14 @@ +let + nixpkgs = fetchTarball "https://github.com/NixOS/nixpkgs/tarball/nixos-24.05";; + pkgs = import nixpkgs { config = {}; overlays = []; }; +in + + +pkgs.mkShellNoCC { + packages = with pkgs; [ + cmake + ninja + llvmPackages_latest.llvm + ]; +stdenv = pkgs.clangStdenv; +} >From b2bfd33fe7e14b5c8cf423ed11fd7731bb9e9511 Mon Sep 17 00:00:00 2001 From: Omar Ibrahim <[email protected]> Date: Mon, 1 Dec 2025 21:20:57 +0100 Subject: [PATCH 2/5] remove leftover file --- shell.nix | 14 -------------- 1 file changed, 14 deletions(-) delete mode 100644 shell.nix diff --git a/shell.nix b/shell.nix deleted file mode 100644 index c30f6dc7b6928..0000000000000 --- a/shell.nix +++ /dev/null @@ -1,14 +0,0 @@ -let - nixpkgs = fetchTarball "https://github.com/NixOS/nixpkgs/tarball/nixos-24.05";; - pkgs = import nixpkgs { config = {}; overlays = []; }; -in - - -pkgs.mkShellNoCC { - packages = with pkgs; [ - cmake - ninja - llvmPackages_latest.llvm - ]; -stdenv = pkgs.clangStdenv; -} >From 8527cb5d3d667a27851df8afdf6799a2605d5d89 Mon Sep 17 00:00:00 2001 From: Omar Ibrahim <[email protected]> Date: Mon, 1 Dec 2025 21:26:16 +0100 Subject: [PATCH 3/5] use builder right away --- clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index 8ebabf704bc80..e5654c463b3c7 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -729,16 +729,16 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, case X86::BI__builtin_ia32_prolq128: case X86::BI__builtin_ia32_prolq256: case X86::BI__builtin_ia32_prolq512: - return emitX86FunnelShift(this->getBuilder(), getLoc(expr->getExprLoc()), - ops[0], ops[0], ops[1], false); + return emitX86FunnelShift(builder, getLoc(expr->getExprLoc()), ops[0], + ops[0], ops[1], false); case X86::BI__builtin_ia32_prord128: case X86::BI__builtin_ia32_prord256: case X86::BI__builtin_ia32_prord512: case X86::BI__builtin_ia32_prorq128: case X86::BI__builtin_ia32_prorq256: case X86::BI__builtin_ia32_prorq512: - return emitX86FunnelShift(this->getBuilder(), getLoc(expr->getExprLoc()), - ops[0], ops[0], ops[1], true); + return emitX86FunnelShift(builder, getLoc(expr->getExprLoc()), ops[0], + ops[0], ops[1], true); case X86::BI__builtin_ia32_selectb_128: case X86::BI__builtin_ia32_selectb_256: case X86::BI__builtin_ia32_selectb_512: >From 4dc43431dc0a5ab02a1715c90490ed42f5ac20a5 Mon Sep 17 00:00:00 2001 From: Omar Ibrahim <[email protected]> Date: Mon, 1 Dec 2025 21:30:11 +0100 Subject: [PATCH 4/5] address style comments --- clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c | 8 ++++---- clang/test/CIR/CodeGenBuiltins/X86/xop-builtins.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c index 99068b7df6e40..20fe11c50d565 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c @@ -233,7 +233,7 @@ __m512i test_mm512_ror_epi32(__m512i __A) { // CIR-LABEL: test_mm512_ror_epi32 // CIR: cir.cast integral %{{.*}} : !s32i -> !u32i // CIR: cir.vec.splat %{{.*}} : !u32i, !cir.vector<16 x !u32i> - // CIR: cir.call_llvm_intrinsic "fshr" {{%.*}}: (!cir.vector<16 x !s32i>, !cir.vector<16 x !s32i>, !cir.vector<16 x !u32i>) -> !cir.vector<16 x !s32i> + // CIR: cir.call_llvm_intrinsic "fshr" %{{.*}}: (!cir.vector<16 x !s32i>, !cir.vector<16 x !s32i>, !cir.vector<16 x !u32i>) -> !cir.vector<16 x !s32i> // LLVM-LABEL: test_mm512_ror_epi32 // LLVM: %[[CASTED_VAR:.*]] = bitcast <8 x i64> %{{.*}} to <16 x i32> @@ -250,14 +250,14 @@ __m512i test_mm512_ror_epi64(__m512i __A) { // CIR: cir.cast integral %{{.*}} : !s32i -> !u32i // CIR: cir.cast integral %{{.*}} : !u32i -> !u64i // CIR: cir.vec.splat %{{.*}} : !u64i, !cir.vector<8 x !u64i> - // CIR: cir.call_llvm_intrinsic "fshr" {{%.*}}: (!cir.vector<8 x !s64i>, !cir.vector<8 x !s64i>, !cir.vector<8 x !u64i>) -> !cir.vector<8 x !s64i> + // CIR: cir.call_llvm_intrinsic "fshr" %{{.*}}: (!cir.vector<8 x !s64i>, !cir.vector<8 x !s64i>, !cir.vector<8 x !u64i>) -> !cir.vector<8 x !s64i> // LLVM-LABEL: test_mm512_ror_epi64 - // LLVM: %[[VAR:.*]] = load <8 x i64>, ptr {{%.*}}, align 64 + // LLVM: %[[VAR:.*]] = load <8 x i64>, ptr %{{.*}}, align 64 // LLVM: call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %[[VAR]], <8 x i64> %[[VAR]], <8 x i64> splat (i64 5)) // OGCG-LABEL: test_mm512_ror_epi64 - // OGCG: %[[VAR:.*]] = load <8 x i64>, ptr {{%.*}}, align 64 + // OGCG: %[[VAR:.*]] = load <8 x i64>, ptr %{{.*}}, align 64 // OGCG: call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %[[VAR]], <8 x i64> %[[VAR]], <8 x i64> splat (i64 5)) return _mm512_ror_epi64(__A, 5); } diff --git a/clang/test/CIR/CodeGenBuiltins/X86/xop-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/xop-builtins.c index c10fc1ca486df..0aaba7b46327d 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/xop-builtins.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/xop-builtins.c @@ -31,7 +31,7 @@ __m128i test_mm_roti_epi8(__m128i a) { // CIR-LABEL: test_mm_roti_epi8 // CIR: cir.vec.splat %{{.*}} : !{{[us]}}8i, !cir.vector<16 x !{{[us]}}8i> - // CIR: cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<16 x !{{[su]}}8i>, !cir.vector<16 x !{{[su]}}8i>, !cir.vector<16 x !{{[su]}}8i>) -> !cir.vector<16 x !{{[su]}}8i> + // CIR: cir.call_llvm_intrinsic "fshl" %{{.*}} : (!cir.vector<16 x !{{[su]}}8i>, !cir.vector<16 x !{{[su]}}8i>, !cir.vector<16 x !{{[su]}}8i>) -> !cir.vector<16 x !{{[su]}}8i> // LLVM-LABEL: test_mm_roti_epi8 // LLVM: %[[CASTED_VAR:.*]] = bitcast <2 x i64> %{{.*}} to <16 x i8> @@ -47,7 +47,7 @@ __m128i test_mm_roti_epi16(__m128i a) { // CIR-LABEL: test_mm_roti_epi16 // CIR: cir.cast integral %{{.*}} : !u8i -> !u16i // CIR: cir.vec.splat %{{.*}} : !{{[us]}}16i, !cir.vector<8 x !u16i> - // CIR: cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<8 x !{{[su]}}16i>, !cir.vector<8 x !{{[su]}}16i>, !cir.vector<8 x !u16i>) -> !cir.vector<8 x !{{[su]}}16i> + // CIR: cir.call_llvm_intrinsic "fshl" %{{.*}} : (!cir.vector<8 x !{{[su]}}16i>, !cir.vector<8 x !{{[su]}}16i>, !cir.vector<8 x !u16i>) -> !cir.vector<8 x !{{[su]}}16i> // LLVM-LABEL: test_mm_roti_epi16 // LLVM: %[[CASTED_VAR:.*]] = bitcast <2 x i64> %{{.*}} to <8 x i16> @@ -63,7 +63,7 @@ __m128i test_mm_roti_epi32(__m128i a) { // CIR-LABEL: test_mm_roti_epi32 // CIR: cir.cast integral %{{.*}} : !u8i -> !u32i // CIR: cir.vec.splat %{{.*}} : !{{[us]}}32i, !cir.vector<4 x !u32i> - // CIR: cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<4 x !{{[su]}}32i>, !cir.vector<4 x !{{[su]}}32i>, !cir.vector<4 x !u32i>) -> !cir.vector<4 x !{{[su]}}32i> + // CIR: cir.call_llvm_intrinsic "fshl" %{{.*}} : (!cir.vector<4 x !{{[su]}}32i>, !cir.vector<4 x !{{[su]}}32i>, !cir.vector<4 x !u32i>) -> !cir.vector<4 x !{{[su]}}32i> // LLVM-LABEL: test_mm_roti_epi32 // LLVM: %[[CASTED_VAR:.*]] = bitcast <2 x i64> %{{.*}} to <4 x i32> @@ -79,7 +79,7 @@ __m128i test_mm_roti_epi64(__m128i a) { // CIR-LABEL: test_mm_roti_epi64 // CIR: cir.cast integral %{{.*}} : !u8i -> !u64i // CIR: cir.vec.splat %{{.*}} : !u64i, !cir.vector<2 x !u64i> - // CIR: cir.call_llvm_intrinsic "fshl" {{.*}} : (!cir.vector<2 x !{{[su]}}64i>, !cir.vector<2 x !{{[su]}}64i>, !cir.vector<2 x !u64i>) -> !cir.vector<2 x !s64i> + // CIR: cir.call_llvm_intrinsic "fshl" %{{.*}} : (!cir.vector<2 x !{{[su]}}64i>, !cir.vector<2 x !{{[su]}}64i>, !cir.vector<2 x !u64i>) -> !cir.vector<2 x !s64i> // LLVM-LABEL: test_mm_roti_epi64 // LLVM: %[[VAR:.*]] = load <2 x i64>, ptr %{{.*}}, align 16 >From 1dbd13c1406d5a136d6aa66bf270ce6d599d924d Mon Sep 17 00:00:00 2001 From: Omar Ibrahim <[email protected]> Date: Mon, 1 Dec 2025 21:38:04 +0100 Subject: [PATCH 5/5] revert unrelated test cases changes --- .../CIR/CodeGenBuiltins/X86/avx512f-builtins.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c index 20fe11c50d565..0c00250e96363 100644 --- a/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c +++ b/clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c @@ -18,12 +18,12 @@ __m512 test_mm512_undefined(void) { // CIR-LABEL: _mm512_undefined // CIR: %[[A:.*]] = cir.const #cir.zero : !cir.vector<8 x !cir.double> - // CIR: cir.cast bitcast %[[A]] : !cir.vector<8 x !cir.double> -> !cir.vector<16 x !cir.float> + // CIR: %{{.*}} = cir.cast bitcast %[[A]] : !cir.vector<8 x !cir.double> -> !cir.vector<16 x !cir.float> // CIR: cir.return %{{.*}} : !cir.vector<16 x !cir.float> // LLVM-LABEL: test_mm512_undefined // LLVM: store <16 x float> zeroinitializer, ptr %[[A:.*]], align 64 - // LLVM: load <16 x float>, ptr %[[A]], align 64 + // LLVM: %{{.*}} = load <16 x float>, ptr %[[A]], align 64 // LLVM: ret <16 x float> %{{.*}} // OGCG-LABEL: test_mm512_undefined @@ -34,12 +34,12 @@ __m512 test_mm512_undefined(void) { __m512 test_mm512_undefined_ps(void) { // CIR-LABEL: _mm512_undefined_ps // CIR: %[[A:.*]] = cir.const #cir.zero : !cir.vector<8 x !cir.double> - // CIR: cir.cast bitcast %[[A]] : !cir.vector<8 x !cir.double> -> !cir.vector<16 x !cir.float> + // CIR: %{{.*}} = cir.cast bitcast %[[A]] : !cir.vector<8 x !cir.double> -> !cir.vector<16 x !cir.float> // CIR: cir.return %{{.*}} : !cir.vector<16 x !cir.float> // LLVM-LABEL: test_mm512_undefined_ps // LLVM: store <16 x float> zeroinitializer, ptr %[[A:.*]], align 64 - // LLVM: load <16 x float>, ptr %[[A]], align 64 + // LLVM: %{{.*}} = load <16 x float>, ptr %[[A]], align 64 // LLVM: ret <16 x float> %{{.*}} // OGCG-LABEL: test_mm512_undefined_ps @@ -49,12 +49,12 @@ __m512 test_mm512_undefined_ps(void) { __m512d test_mm512_undefined_pd(void) { // CIR-LABEL: _mm512_undefined_pd - // CIR: cir.const #cir.zero : !cir.vector<8 x !cir.double> + // CIR: %{{.*}} = cir.const #cir.zero : !cir.vector<8 x !cir.double> // CIR: cir.return %{{.*}} : !cir.vector<8 x !cir.double> // LLVM-LABEL: test_mm512_undefined_pd // LLVM: store <8 x double> zeroinitializer, ptr %[[A:.*]], align 64 - // LLVM: load <8 x double>, ptr %[[A]], align 64 + // LLVM: %{{.*}} = load <8 x double>, ptr %[[A]], align 64 // LLVM: ret <8 x double> %{{.*}} // OGCG-LABEL: test_mm512_undefined_pd @@ -64,13 +64,13 @@ __m512d test_mm512_undefined_pd(void) { __m512i test_mm512_undefined_epi32(void) { // CIR-LABEL: _mm512_undefined_epi32 - // CIR: cir.const #cir.zero : !cir.vector<8 x !cir.double> - // CIR: cir.cast bitcast %[[A]] : !cir.vector<8 x !cir.double> -> !cir.vector<8 x !s64i> + // CIR: %[[A:.*]] = cir.const #cir.zero : !cir.vector<8 x !cir.double> + // CIR: %{{.*}} = cir.cast bitcast %[[A]] : !cir.vector<8 x !cir.double> -> !cir.vector<8 x !s64i> // CIR: cir.return %{{.*}} : !cir.vector<8 x !s64i> // LLVM-LABEL: test_mm512_undefined_epi32 // LLVM: store <8 x i64> zeroinitializer, ptr %[[A:.*]], align 64 - // LLVM: load <8 x i64>, ptr %[[A]], align 64 + // LLVM: %{{.*}} = load <8 x i64>, ptr %[[A]], align 64 // LLVM: ret <8 x i64> %{{.*}} // OGCG-LABEL: test_mm512_undefined_epi32 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
