================
@@ -887,7 +921,30 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned
builtinID,
case X86::BI__builtin_ia32_extractf64x2_256_mask:
case X86::BI__builtin_ia32_extracti64x2_256_mask:
case X86::BI__builtin_ia32_extractf64x2_512_mask:
- case X86::BI__builtin_ia32_extracti64x2_512_mask:
+ case X86::BI__builtin_ia32_extracti64x2_512_mask: {
+ mlir::Location loc = getLoc(expr->getExprLoc());
+ cir::VectorType dstTy =
cast<cir::VectorType>(convertType(expr->getType()));
+ unsigned numElts = dstTy.getSize();
+ unsigned srcNumElts = cast<cir::VectorType>(ops[0].getType()).getSize();
+ unsigned subVectors = srcNumElts / numElts;
+ assert(llvm::isPowerOf2_32(subVectors) && "Expected power of 2
subvectors");
+ unsigned index =
+ ops[1].getDefiningOp<cir::ConstantOp>().getIntValue().getZExtValue();
+
+ index &= subVectors - 1; // Remove any extra bits.
+ index *= numElts;
+
+ int64_t indices[16];
+ std::iota(indices, indices + numElts, index);
+
+ mlir::Value zero = builder.getNullValue(ops[0].getType(), loc);
+ mlir::Value res =
+ builder.createVecShuffle(loc, ops[0], zero, ArrayRef(indices,
numElts));
----------------
andykaylor wrote:
```suggestion
builder.createVecShuffle(loc, ops[0], poison, ArrayRef(indices,
numElts));
```
https://github.com/llvm/llvm-project/pull/170427
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