https://github.com/YGGkk updated https://github.com/llvm/llvm-project/pull/171621
>From b2a8864d269f727ae4e85188d68a3a1230f43d0b Mon Sep 17 00:00:00 2001 From: Zhihui Yang <[email protected]> Date: Wed, 10 Dec 2025 05:46:30 -0800 Subject: [PATCH 1/5] [CIR][X86] Add support for alignd builtins --- clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 23 +++++++- .../CIR/CodeGenBuiltins/X86/alignd-builtins.c | 55 +++++++++++++++++++ 2 files changed, 75 insertions(+), 3 deletions(-) create mode 100644 clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index 62836ce0f7537..6b4e06966b828 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -1154,9 +1154,6 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, case X86::BI__builtin_ia32_palignr128: case X86::BI__builtin_ia32_palignr256: case X86::BI__builtin_ia32_palignr512: - case X86::BI__builtin_ia32_alignd128: - case X86::BI__builtin_ia32_alignd256: - case X86::BI__builtin_ia32_alignd512: case X86::BI__builtin_ia32_alignq128: case X86::BI__builtin_ia32_alignq256: case X86::BI__builtin_ia32_alignq512: @@ -1182,6 +1179,26 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, std::string("unimplemented X86 builtin call: ") + getContext().BuiltinInfo.getName(builtinID)); return {}; + case X86::BI__builtin_ia32_alignd128: + case X86::BI__builtin_ia32_alignd256: + case X86::BI__builtin_ia32_alignd512: { + unsigned numElts = cast<cir::VectorType>(ops[0].getType()).getSize(); + unsigned shiftVal = + ops[2].getDefiningOp<cir::ConstantOp>().getIntValue().getZExtValue() & + 0xff; + + // Mask the shift amount to width of a vector. + shiftVal &= numElts - 1; + + SmallVector<mlir::Attribute, 16> indices; + mlir::Type i32Ty = builder.getSInt32Ty(); + for (unsigned i = 0; i != numElts; ++i) + indices.push_back( + cir::IntAttr::get(i32Ty, i + shiftVal)); + + return builder.createVecShuffle(getLoc(expr->getExprLoc()), ops[0], ops[1], + indices); + } case X86::BI__builtin_ia32_kshiftliqi: case X86::BI__builtin_ia32_kshiftlihi: case X86::BI__builtin_ia32_kshiftlisi: diff --git a/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c new file mode 100644 index 0000000000000..73c21d6f3d802 --- /dev/null +++ b/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c @@ -0,0 +1,55 @@ +// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s +// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s +// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s +// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s + +// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s +// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s +// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s +// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s + +// RUN: %clang_cc1 -x c -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG +// RUN: %clang_cc1 -x c++ -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG + +#include <immintrin.h> + +__v4si test_builtin_ia32_alignd128() +{ + // CIR-LABEL: _builtin_ia32_alignd128 + // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<4 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !s32i> + + // LLVM-LABEL: test_builtin_ia32_alignd128 + // LLVM: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + + // OGCG-LABEL: test_builtin_ia32_alignd128 + // OGCG: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + __v4si vec1 = {0, 1, 2, 3}; + __v4si vec2 = {4, 5, 6, 7}; + return __builtin_ia32_alignd128(vec1, vec2, 0); +} + +__v8si test_builtin_ia32_alignd256() +{ + // CIR-LABEL: _builtin_ia32_alignd256 + // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<8 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !s32i> + // LLVM-LABEL: test_builtin_ia32_alignd256 + // LLVM: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + // OGCG-LABEL: test_builtin_ia32_alignd256 + // OGCG: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + __v8si vec1 = {0, 1, 2, 3, 4, 5, 6, 7}; + __v8si vec2 = {8, 9, 10, 11, 12, 13, 14, 15}; + return __builtin_ia32_alignd256(vec1, vec2, 0); +} + +__v16si test_builtin_ia32_alignd512() +{ + // CIR-LABEL: _builtin_ia32_alignd512 + // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<16 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i, #cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i] : !cir.vector<16 x !s32i> + // LLVM-LABEL: test_builtin_ia32_alignd512 + // LLVM: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + // OGCG-LABEL: test_builtin_ia32_alignd512 + // OGCG: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + __v16si vec1 = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; + __v16si vec2 = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}; + return __builtin_ia32_alignd512(vec1, vec2, 0); +} \ No newline at end of file >From 62df051cc61ee0fec3b5d7e834ed9b3213ea33f7 Mon Sep 17 00:00:00 2001 From: Zhihui Yang <[email protected]> Date: Wed, 10 Dec 2025 05:46:30 -0800 Subject: [PATCH 2/5] [CIR][X86] Add support for alignd builtins --- clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 22 +++++++- .../CIR/CodeGenBuiltins/X86/alignd-builtins.c | 55 +++++++++++++++++++ 2 files changed, 74 insertions(+), 3 deletions(-) create mode 100644 clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index 62836ce0f7537..a22a23b8c4c72 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -1154,9 +1154,6 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, case X86::BI__builtin_ia32_palignr128: case X86::BI__builtin_ia32_palignr256: case X86::BI__builtin_ia32_palignr512: - case X86::BI__builtin_ia32_alignd128: - case X86::BI__builtin_ia32_alignd256: - case X86::BI__builtin_ia32_alignd512: case X86::BI__builtin_ia32_alignq128: case X86::BI__builtin_ia32_alignq256: case X86::BI__builtin_ia32_alignq512: @@ -1182,6 +1179,25 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, std::string("unimplemented X86 builtin call: ") + getContext().BuiltinInfo.getName(builtinID)); return {}; + case X86::BI__builtin_ia32_alignd128: + case X86::BI__builtin_ia32_alignd256: + case X86::BI__builtin_ia32_alignd512: { + unsigned numElts = cast<cir::VectorType>(ops[0].getType()).getSize(); + unsigned shiftVal = + ops[2].getDefiningOp<cir::ConstantOp>().getIntValue().getZExtValue() & + 0xff; + + // Mask the shift amount to width of a vector. + shiftVal &= numElts - 1; + + SmallVector<mlir::Attribute, 16> indices; + mlir::Type i32Ty = builder.getSInt32Ty(); + for (unsigned i = 0; i != numElts; ++i) + indices.push_back(cir::IntAttr::get(i32Ty, i + shiftVal)); + + return builder.createVecShuffle(getLoc(expr->getExprLoc()), ops[0], ops[1], + indices); + } case X86::BI__builtin_ia32_kshiftliqi: case X86::BI__builtin_ia32_kshiftlihi: case X86::BI__builtin_ia32_kshiftlisi: diff --git a/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c new file mode 100644 index 0000000000000..73c21d6f3d802 --- /dev/null +++ b/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c @@ -0,0 +1,55 @@ +// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s +// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s +// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s +// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s + +// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s +// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s +// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s +// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s + +// RUN: %clang_cc1 -x c -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG +// RUN: %clang_cc1 -x c++ -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG + +#include <immintrin.h> + +__v4si test_builtin_ia32_alignd128() +{ + // CIR-LABEL: _builtin_ia32_alignd128 + // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<4 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !s32i> + + // LLVM-LABEL: test_builtin_ia32_alignd128 + // LLVM: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + + // OGCG-LABEL: test_builtin_ia32_alignd128 + // OGCG: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + __v4si vec1 = {0, 1, 2, 3}; + __v4si vec2 = {4, 5, 6, 7}; + return __builtin_ia32_alignd128(vec1, vec2, 0); +} + +__v8si test_builtin_ia32_alignd256() +{ + // CIR-LABEL: _builtin_ia32_alignd256 + // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<8 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !s32i> + // LLVM-LABEL: test_builtin_ia32_alignd256 + // LLVM: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + // OGCG-LABEL: test_builtin_ia32_alignd256 + // OGCG: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + __v8si vec1 = {0, 1, 2, 3, 4, 5, 6, 7}; + __v8si vec2 = {8, 9, 10, 11, 12, 13, 14, 15}; + return __builtin_ia32_alignd256(vec1, vec2, 0); +} + +__v16si test_builtin_ia32_alignd512() +{ + // CIR-LABEL: _builtin_ia32_alignd512 + // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<16 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i, #cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i] : !cir.vector<16 x !s32i> + // LLVM-LABEL: test_builtin_ia32_alignd512 + // LLVM: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + // OGCG-LABEL: test_builtin_ia32_alignd512 + // OGCG: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + __v16si vec1 = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; + __v16si vec2 = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}; + return __builtin_ia32_alignd512(vec1, vec2, 0); +} \ No newline at end of file >From 24d193bee62a8012caaa57eda1a603c5a21caf62 Mon Sep 17 00:00:00 2001 From: Zhihui Yang <[email protected]> Date: Thu, 11 Dec 2025 00:33:58 -0800 Subject: [PATCH 3/5] [CIR][X86] Add support for align builtins --- clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 22 ++++- .../CIR/CodeGenBuiltins/X86/align-builtins.c | 94 +++++++++++++++++++ 2 files changed, 115 insertions(+), 1 deletion(-) create mode 100644 clang/test/CIR/CodeGenBuiltins/X86/align-builtins.c diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index 75bf25b20f1af..b08f2edb0bf03 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -1214,12 +1214,32 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, case X86::BI__builtin_ia32_palignr128: case X86::BI__builtin_ia32_palignr256: case X86::BI__builtin_ia32_palignr512: + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented X86 builtin call: ") + + getContext().BuiltinInfo.getName(builtinID)); + return {}; case X86::BI__builtin_ia32_alignd128: case X86::BI__builtin_ia32_alignd256: case X86::BI__builtin_ia32_alignd512: case X86::BI__builtin_ia32_alignq128: case X86::BI__builtin_ia32_alignq256: - case X86::BI__builtin_ia32_alignq512: + case X86::BI__builtin_ia32_alignq512: { + unsigned numElts = cast<cir::VectorType>(ops[0].getType()).getSize(); + unsigned shiftVal = + ops[2].getDefiningOp<cir::ConstantOp>().getIntValue().getZExtValue() & + 0xff; + + // Mask the shift amount to width of a vector. + shiftVal &= numElts - 1; + + SmallVector<mlir::Attribute, 16> indices; + mlir::Type i32Ty = builder.getSInt32Ty(); + for (unsigned i = 0; i != numElts; ++i) + indices.push_back(cir::IntAttr::get(i32Ty, i + shiftVal)); + + return builder.createVecShuffle(getLoc(expr->getExprLoc()), ops[0], ops[1], + indices); + } case X86::BI__builtin_ia32_shuf_f32x4_256: case X86::BI__builtin_ia32_shuf_f64x2_256: case X86::BI__builtin_ia32_shuf_i32x4_256: diff --git a/clang/test/CIR/CodeGenBuiltins/X86/align-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/align-builtins.c new file mode 100644 index 0000000000000..e665a59c0bca1 --- /dev/null +++ b/clang/test/CIR/CodeGenBuiltins/X86/align-builtins.c @@ -0,0 +1,94 @@ +// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s +// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s +// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s +// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s + +// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s +// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s +// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s +// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s + +// RUN: %clang_cc1 -x c -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG +// RUN: %clang_cc1 -x c++ -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG + +#include <immintrin.h> + +__v4si test_builtin_ia32_alignd128() +{ + // CIR-LABEL: _builtin_ia32_alignd128 + // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<4 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !s32i> + + // LLVM-LABEL: test_builtin_ia32_alignd128 + // LLVM: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + + // OGCG-LABEL: test_builtin_ia32_alignd128 + // OGCG: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + __v4si vec1 = {0, 1, 2, 3}; + __v4si vec2 = {4, 5, 6, 7}; + return __builtin_ia32_alignd128(vec1, vec2, 0); +} + +__v8si test_builtin_ia32_alignd256() +{ + // CIR-LABEL: _builtin_ia32_alignd256 + // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<8 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !s32i> + // LLVM-LABEL: test_builtin_ia32_alignd256 + // LLVM: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + // OGCG-LABEL: test_builtin_ia32_alignd256 + // OGCG: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + __v8si vec1 = {0, 1, 2, 3, 4, 5, 6, 7}; + __v8si vec2 = {8, 9, 10, 11, 12, 13, 14, 15}; + return __builtin_ia32_alignd256(vec1, vec2, 0); +} + +__v16si test_builtin_ia32_alignd512() +{ + // CIR-LABEL: _builtin_ia32_alignd512 + // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<16 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i, #cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i] : !cir.vector<16 x !s32i> + // LLVM-LABEL: test_builtin_ia32_alignd512 + // LLVM: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + // OGCG-LABEL: test_builtin_ia32_alignd512 + // OGCG: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + __v16si vec1 = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; + __v16si vec2 = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}; + return __builtin_ia32_alignd512(vec1, vec2, 0); +} + +__v2di test_builtin_ia32_alignq128() +{ + // CIR-LABEL: _builtin_ia32_alignq128 + // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<2 x !s64i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i] : !cir.vector<2 x !s64i> + // LLVM-LABEL: test_builtin_ia32_alignq128 + // LLVM: shufflevector <2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i32> <i32 0, i32 1> + // OGCG-LABEL: test_builtin_ia32_alignq128 + // OGCG: shufflevector <2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i32> <i32 0, i32 1> + __v2di vec1 = {0, 1}; + __v2di vec2 = {2, 3}; + return __builtin_ia32_alignq128(vec1, vec2, 0); +} + +__v4di test_builtin_ia32_alignq256() +{ + // CIR-LABEL: _builtin_ia32_alignq256 + // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<4 x !s64i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !s64i> + // LLVM-LABEL: test_builtin_ia32_alignq256 + // LLVM: shufflevector <4 x i64> %{{.*}}, <4 x i64> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + // OGCG-LABEL: test_builtin_ia32_alignq256 + // OGCG: shufflevector <4 x i64> %{{.*}}, <4 x i64> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + __v4di vec1 = {0, 1, 2, 3}; + __v4di vec2 = {4, 5, 6, 7}; + return __builtin_ia32_alignq256(vec1, vec2, 0); +} + +__v8di test_builtin_ia32_alignq512() +{ + // CIR-LABEL: _builtin_ia32_alignq512 + // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<8 x !s64i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !s64i> + // LLVM-LABEL: test_builtin_ia32_alignq512 + // LLVM: shufflevector <8 x i64> %{{.*}}, <8 x i64> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + // OGCG-LABEL: test_builtin_ia32_alignq512 + // OGCG: shufflevector <8 x i64> %{{.*}}, <8 x i64> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + __v8di vec1 = {0, 1, 2, 3, 4, 5, 6, 7}; + __v8di vec2 = {8, 9, 10, 11, 12, 13, 14, 15}; + return __builtin_ia32_alignq512(vec1, vec2, 0); +} >From af55858dcf241ac1e649e4d805f27419115e003e Mon Sep 17 00:00:00 2001 From: Zhihui Yang <[email protected]> Date: Thu, 11 Dec 2025 16:40:45 +0800 Subject: [PATCH 4/5] Delete repeated alignd-builtins.c --- .../CIR/CodeGenBuiltins/X86/alignd-builtins.c | 55 ------------------- 1 file changed, 55 deletions(-) delete mode 100644 clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c diff --git a/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c b/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c deleted file mode 100644 index 73c21d6f3d802..0000000000000 --- a/clang/test/CIR/CodeGenBuiltins/X86/alignd-builtins.c +++ /dev/null @@ -1,55 +0,0 @@ -// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s -// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s -// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-cir -o %t.cir %s -// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s - -// RUN: %clang_cc1 -x c -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s -// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s -// RUN: %clang_cc1 -x c++ -ffreestanding -triple x86_64-unknown-linux -target-feature +avx512vl -Wno-implicit-function-declaration -fclangir -emit-llvm -o %t.ll %s -// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s - -// RUN: %clang_cc1 -x c -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG -// RUN: %clang_cc1 -x c++ -ffreestanding -triple=x86_64-unknown-linux -target-feature +avx512vl -emit-llvm -Wall -Werror %s -o - | FileCheck %s -check-prefix=OGCG - -#include <immintrin.h> - -__v4si test_builtin_ia32_alignd128() -{ - // CIR-LABEL: _builtin_ia32_alignd128 - // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<4 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i] : !cir.vector<4 x !s32i> - - // LLVM-LABEL: test_builtin_ia32_alignd128 - // LLVM: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> - - // OGCG-LABEL: test_builtin_ia32_alignd128 - // OGCG: shufflevector <4 x i32> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> <i32 0, i32 1, i32 2, i32 3> - __v4si vec1 = {0, 1, 2, 3}; - __v4si vec2 = {4, 5, 6, 7}; - return __builtin_ia32_alignd128(vec1, vec2, 0); -} - -__v8si test_builtin_ia32_alignd256() -{ - // CIR-LABEL: _builtin_ia32_alignd256 - // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<8 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i] : !cir.vector<8 x !s32i> - // LLVM-LABEL: test_builtin_ia32_alignd256 - // LLVM: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> - // OGCG-LABEL: test_builtin_ia32_alignd256 - // OGCG: shufflevector <8 x i32> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> - __v8si vec1 = {0, 1, 2, 3, 4, 5, 6, 7}; - __v8si vec2 = {8, 9, 10, 11, 12, 13, 14, 15}; - return __builtin_ia32_alignd256(vec1, vec2, 0); -} - -__v16si test_builtin_ia32_alignd512() -{ - // CIR-LABEL: _builtin_ia32_alignd512 - // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<16 x !s32i>) [#cir.int<0> : !s32i, #cir.int<1> : !s32i, #cir.int<2> : !s32i, #cir.int<3> : !s32i, #cir.int<4> : !s32i, #cir.int<5> : !s32i, #cir.int<6> : !s32i, #cir.int<7> : !s32i, #cir.int<8> : !s32i, #cir.int<9> : !s32i, #cir.int<10> : !s32i, #cir.int<11> : !s32i, #cir.int<12> : !s32i, #cir.int<13> : !s32i, #cir.int<14> : !s32i, #cir.int<15> : !s32i] : !cir.vector<16 x !s32i> - // LLVM-LABEL: test_builtin_ia32_alignd512 - // LLVM: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> - // OGCG-LABEL: test_builtin_ia32_alignd512 - // OGCG: shufflevector <16 x i32> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> - __v16si vec1 = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; - __v16si vec2 = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}; - return __builtin_ia32_alignd512(vec1, vec2, 0); -} \ No newline at end of file >From 6fb0ad4ade4573effeec028cf035db6be355dd6e Mon Sep 17 00:00:00 2001 From: Zhihui Yang <[email protected]> Date: Thu, 11 Dec 2025 00:48:42 -0800 Subject: [PATCH 5/5] fix some duplicate code --- clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp index 2db995923051a..b08f2edb0bf03 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp @@ -1262,25 +1262,6 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, std::string("unimplemented X86 builtin call: ") + getContext().BuiltinInfo.getName(builtinID)); return {}; - case X86::BI__builtin_ia32_alignd128: - case X86::BI__builtin_ia32_alignd256: - case X86::BI__builtin_ia32_alignd512: { - unsigned numElts = cast<cir::VectorType>(ops[0].getType()).getSize(); - unsigned shiftVal = - ops[2].getDefiningOp<cir::ConstantOp>().getIntValue().getZExtValue() & - 0xff; - - // Mask the shift amount to width of a vector. - shiftVal &= numElts - 1; - - SmallVector<mlir::Attribute, 16> indices; - mlir::Type i32Ty = builder.getSInt32Ty(); - for (unsigned i = 0; i != numElts; ++i) - indices.push_back(cir::IntAttr::get(i32Ty, i + shiftVal)); - - return builder.createVecShuffle(getLoc(expr->getExprLoc()), ops[0], ops[1], - indices); - } case X86::BI__builtin_ia32_kshiftliqi: case X86::BI__builtin_ia32_kshiftlihi: case X86::BI__builtin_ia32_kshiftlisi: _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
